Patents by Inventor Akira Tabata
Akira Tabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240129686Abstract: A display control apparatus for controlling display of a display device that a user can wear acquires speech collected by a plurality of microphones, estimates a sound-arrival direction of the acquired speech, and generates a text image corresponding to the acquired speech. The display control apparatus determines an adjustment amount of a display position of the text image on the display unit of the display device based on a detection result of at least one of an operation by the user and a state of the display device. Then, the display control apparatus displays the generated text image at a display position in the display unit, the display position being determined in accordance with the estimated sound-arrival direction and the determined adjustment amount.Type: ApplicationFiled: December 19, 2023Publication date: April 18, 2024Applicants: Pixie Dust Technologies, Inc., Sumitomo Pharma Co., Ltd.Inventors: Megumi TABATA, Haruki NISHIMURA, Akira ENDO, Yasuhiro HABARA, Masaki GOMI, Yudai TAIRA
-
Publication number: 20240119684Abstract: A display control apparatus for controlling display of a display device acquires speech collected by a plurality of microphones and estimates a sound-arrival direction of the acquired speech. Then, the display control apparatus causes a text image corresponding to the acquired speech to be displayed in a predetermined text display area in a display unit of the display device, and causes a symbol image associated with the text image to be displayed at a display position in the display unit, the display position corresponding to the estimated sound-arrival direction.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Applicants: Pixie Dust Technologies, Inc., Sumitomo Pharma Co., Ltd.Inventors: Megumi TABATA, Haruki NISHIMURA, Akira ENDO, Yasuhiro HABARA, Masaki GOMI, Yudai TAIRA
-
Publication number: 20240096145Abstract: A noise generation cause identifying method and a noise generation cause identifying device are provided. A response correcting process corrects a sound signal obtained through a sound signal obtaining process based on obtained model information so that a frequency response of the obtained sound signal approaches a frequency response of a learning sound signal. A variable obtaining process obtains a variable output from a map by inputting the corrected sound signal to the map. A cause identifying process identifies a generation cause of a sound picked up by a microphone using the variable obtained through the variable obtaining process.Type: ApplicationFiled: April 27, 2023Publication date: March 21, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinichi TAKEUCHI, Atsushi TABATA, Mitsuo OKUBO, Shingo NORITAKE, Akira MURAKAMI, Ryo YANAGAWA
-
Publication number: 20060002954Abstract: The object of the present invention is to provide a composition which is capable of going into erythrocyte or into cells, trapping not only oxygen radicals but also hydroxyl radicals, and preventing or improving various symptoms including hypertension, excessive sensitivity to cold, diabetes, Parkinson's disease, menstrual disorder, brain infarct, atopic dermatitis, hay fever, articular rheumatism, autonomic ataxia, and the like by oral intake. The present invention relates to an invention of a composition trapping radicals in organism comprising the steps of: roasting soy bean, wheat germ, adlay, husked rice germ, and rice bran, which are materials at a temperature of 50 to 150° C.Type: ApplicationFiled: June 20, 2005Publication date: January 5, 2006Inventors: Akira Tabata, Takumi Nakamura
-
Patent number: 4824794Abstract: A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.Type: GrantFiled: March 14, 1988Date of Patent: April 25, 1989Assignee: Fujitsu LimitedInventors: Akira Tabata, Motoshu Miyajima, Kazushi Kawaguchi
-
Patent number: 4579625Abstract: A method of producing a complementary semiconductor device having p-type islands and n-type islands in a dielectric isolation structure, including removing a projecting portion of a polycrystalline silicon layer, which is formed at the same time as the formation of an epitaxial silicon layer for one of two types of islands, so as to obtain an almost smooth exposed surface. The smooth surface contributes to the formation of a good masking pattern on the epitaxial silicon layer by a photoetching method, so that mesa portions for islands having exact dimensions are formed at predetermined positions.Type: GrantFiled: September 19, 1984Date of Patent: April 1, 1986Assignee: Fujitsu LimitedInventors: Akira Tabata, Motoshu Miyajima, Yoshifumi Kikuchi
-
Patent number: 4567646Abstract: A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.Type: GrantFiled: November 30, 1984Date of Patent: February 4, 1986Assignee: Fujitsu LimitedInventors: Tamotsu Ishikawa, Hirokazu Tanaka, Akira Tabata
-
Patent number: 4509249Abstract: A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.Type: GrantFiled: September 23, 1983Date of Patent: April 9, 1985Assignee: Fujitsu Ltd.Inventors: Hiroshi Goto, Akira Tabata
-
Patent number: RE34400Abstract: A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.Type: GrantFiled: September 14, 1990Date of Patent: October 5, 1993Assignee: Fujitsu LimitedInventors: Hiroshi Goto, Akira Tabata