Patents by Inventor Akira Tai
Akira Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079606Abstract: A fuel cell separator material includes: a composite material containing electrically conductive particles and a binder resin; and soluble resin layers located on both sides of the composite material.Type: ApplicationFiled: June 29, 2023Publication date: March 7, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, ARISAWA MFG. CO., LTD.Inventors: Takuya HATTORI, Nobuaki NONOYAMA, Makoto TAI, Akira YOSHIDA, Yurina ISHIKAWA, Hideaki DEGUCHI
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Patent number: 8441122Abstract: A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.Type: GrantFiled: August 17, 2010Date of Patent: May 14, 2013Assignee: Denso CorporationInventors: Daisuke Fukuoka, Takanori Teshima, Kuniaki Mamitsu, Ken Sakamoto, Tetsuo Fujii, Akira Tai, Kazuo Akamatsu, Masayoshi Nishihata
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Patent number: 8405218Abstract: In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.Type: GrantFiled: September 22, 2010Date of Patent: March 26, 2013Assignee: DENSO CORPORATIONInventors: Manabu Tomisaka, Michio Kameyama, Terukazu Fukaya, Kazuhito Katoh, Akira Tai, Kazuo Akamatsu, Yoshiko Fukuda, Yuji Fukuda, Mika Ootsuki
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Patent number: 8263490Abstract: A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength.Type: GrantFiled: September 28, 2010Date of Patent: September 11, 2012Assignee: DENSO CORPORATIONInventors: Manabu Tomisaka, Hidetoshi Katou, Yutaka Fukuda, Akira Tai, Kazuo Akamatsu, Yoshiko Fukuda, Yuji Fukuda, Mika Ootsuki
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Publication number: 20110207241Abstract: A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength.Type: ApplicationFiled: September 28, 2010Publication date: August 25, 2011Applicant: DENSO CORPORATIONInventors: Manabu Tomisaka, Hidetoshi Katou, Yutaka Fukuda, Yoshiko Fukuda, Akira Tai, Kazuo Akamatsu
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Publication number: 20110207264Abstract: A method of manufacturing a semiconductor device includes cutting a part of a resin insulating layer formed on a surface of a semiconductor substrate with a cutting tool. The cutting the part of the resin insulating layer includes cutting a portion of the resin insulating layer that has a surface on which a metal layer is disposed. The cutting the portion of the resin insulating layer is performed in such a manner that, in a stress distribution inside the resin insulating layer along an edge portion of the cutting tool and a peripheral portion of the edge portion, a width at 90% of a maximum value is not more than 1.3 ?m.Type: ApplicationFiled: October 15, 2010Publication date: August 25, 2011Applicant: DENSO CORPORATIONInventors: Manabu TOMISAKA, Akira Tai, Kazuo Akamatsu, Yutaka Fukuda, Yoshiko Fukuda, Yuji Fukuda, Mika Ootsuki, Mayu Fukuda
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Publication number: 20110198733Abstract: In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.Type: ApplicationFiled: September 22, 2010Publication date: August 18, 2011Applicant: DENSO CORPORATIONInventors: Manabu Tomisaka, Michio Kameyama, Terukazu Fukaya, Kazuhito Katoh, Yutaka Fukuda, Akira Tai, Kazuo Akamatsu, Yoshiko Fukuda, Yuji Fukuda, Mika Ootsuki, Mayu Fukuda
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Patent number: 7906829Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first insulation separation region and electrically isolated from the first insulation separation region; a semiconductor element disposed in the second insulation separation region; and an electrode connecting to the first insulation separation region for energizing and generating heat in the first insulation separation region. The first insulation separation region functions as a heater so that the semiconductor element in the second insulation separation region is locally heated.Type: GrantFiled: June 6, 2006Date of Patent: March 15, 2011Assignee: Denso CorporationInventor: Akira Tai
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Semiconductor device having semiconductor chip and metal plate and method for manufacturing the same
Publication number: 20110042741Abstract: A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.Type: ApplicationFiled: August 17, 2010Publication date: February 24, 2011Applicant: DENSO CORPORATIONInventors: Daisuke Fukuoka, Takanori Teshima, Kuniaki Mamitsu, Ken Sakamoto, Manabu Tomisaka, Tetsuo Fujii, Akira Tai, Kazuo Akamatsu, Masayoshi Nishihata -
Patent number: 7796442Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.Type: GrantFiled: March 31, 2008Date of Patent: September 14, 2010Assignee: DENSO CORPORATIONInventors: Mitsutaka Katada, Yukiaki Yogo, Akira Tai, Yukihiko Watanabe
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Publication number: 20080239817Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions.Type: ApplicationFiled: March 31, 2008Publication date: October 2, 2008Applicant: DENSO CORPORATIONInventors: Mitsutaka Katada, Yukiaki Yogo, Akira Tai, Yukihiko Watanabe
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Publication number: 20060278950Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first insulation separation region and electrically isolated from the first insulation separation region; a semiconductor element disposed in the second insulation separation region; and an electrode connecting to the first insulation separation region for energizing and generating heat in the first insulation separation region. The first insulation separation region functions as a heater so that the semiconductor element in the second insulation separation region is locally heated.Type: ApplicationFiled: June 6, 2006Publication date: December 14, 2006Applicant: DENSO CORPORATIONInventor: Akira Tai
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Patent number: 7105910Abstract: A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer are surrounded with the trench. The third semiconductor layer is disposed in the trench through a first insulation film disposed on a sidewall of the trench so that the third semiconductor layer contacts the first semiconductor layer at a bottom of the trench.Type: GrantFiled: November 23, 2004Date of Patent: September 12, 2006Assignee: Denso CorporationInventors: Seiichiro Ishio, Akira Tai
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Publication number: 20060071284Abstract: A semiconductor device includes a first insulation film, a second insulation film, a thin film resistor interposed between the insulation films. A predetermined voltage is applied to the thin film resistor so that a current flows through the thin film resistor. When a crack occurs in the insulation films, the thin film resistor is partially destroyed and the resistance of the thin film resistor changes. The crack is detected by measuring the change in resistance of the thin film resistor based on the predetermined voltage and the current flowing through the thin film resistor. Therefore, a crack inspection can be conducted without destruction of the device.Type: ApplicationFiled: September 30, 2005Publication date: April 6, 2006Applicant: DENSO CORPORATIONInventors: Akira Tai, Yoshiaki Nakayama
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Publication number: 20050189617Abstract: A bipolar transistor includes: a base having a first conductive type; an emitter having a second conductive type; a collector having the second conductive type; and a plurality of interceptors for intercepting a carrier path of a current in the base. The carrier path is disposed between the emitter and the collector through the base. Each interceptor is disposed on a shortest distance line of the carrier path in the base between the emitter and the collector. The carrier path is lengthened substantially without increasing the size of the transistor so that the transistor has a high withstand voltage. Further, the carrier path bypasses the interceptors so that the transport efficiency is not reduced substantially.Type: ApplicationFiled: February 25, 2005Publication date: September 1, 2005Inventors: Shoji Mizuno, Akira Tai, Takashi Nakano
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Publication number: 20050110116Abstract: A semiconductor device includes: a semiconductor substrate including a first semiconductor layer, an insulation layer and a second semiconductor layer, which are laminated in this order; a trench penetrating both of the second semiconductor layer and the insulation layer and reaching the first semiconductor layer; and a third semiconductor layer. The trench has a ring shape on a principal surface of the substrate so that a part of the second semiconductor layer and a part of the insulation layer are surrounded with the trench. The third semiconductor layer is disposed in the trench through a first insulation film disposed on a sidewall of the trench so that the third semiconductor layer contacts the first semiconductor layer at a bottom of the trench.Type: ApplicationFiled: November 23, 2004Publication date: May 26, 2005Inventors: Seiichiro Ishio, Akira Tai
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Patent number: 6818942Abstract: In a non-volatile semiconductor storage device, a barrier layer is disposed, via an interlayer isolating film, in an area surrounding a floating gate, including an area adjoining a connecting part of the floating gate, without covering the floating gate. The edge of the barrier layer is, in an overhead view relative to the surface of the semiconductor substrate, disposed at a space of 2 &mgr;m apart from the edge of the floating gate.Type: GrantFiled: December 30, 2002Date of Patent: November 16, 2004Assignee: Denso CorporationInventors: Akira Tai, Shoji Mizuno
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Publication number: 20030136987Abstract: In a non-volatile semiconductor storage device, a barrier layer is disposed, via an interlayer isolating film, in an area surrounding a floating gate, including an area adjoining a connecting part of the floating gate, without covering the floating gate. The edge of the barrier layer is, in an overhead view relative to the surface of the semiconductor substrate, disposed at a space of 2 &mgr;m apart from the edge of the floating gate.Type: ApplicationFiled: December 30, 2002Publication date: July 24, 2003Inventors: Akira Tai, Shoji Mizuno
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Patent number: 5749031Abstract: A developer in use with an image forming apparatus. The developer includes: a developing sleeve which rotates and holds toner on itself so as to develop a latent image on a photoreceptor with the toner; a driving motor for generating a rotational driving force; a drive transmission for transmitting the rotational driving force of the driving motor to the developing cartridge in which the drive transmission has a transmitting state and an untransmitting state; and a shock easing controller or member for easing a shock of transmission of the rotational driving force to the developing sleeve in the transmitting state, in which the shock easing controller or member is provided in at least one of the driving means and the drive transmission means.Type: GrantFiled: June 25, 1996Date of Patent: May 5, 1998Assignee: Konica CorporationInventors: Tadashi Miwa, Hidehiro Kanda, Isao Matsuoka, Toru Makino, Wang Zhoa Yan, Ryoko Yoshikawa, Akira Tai, Naoto Tokutake, Masahiro Shigetomi
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Patent number: 5507182Abstract: A semiconductor accelerometer which can satisfy the requirements of both the sensitivity and the fracture strength without any contrivance for providing viscous liquid and beam stopper material is provided. A casing comprises a stem and a shell. The casing houses an accelerometer chip. The silicon accelerometer chip is of double cantilever beam structure. Each beam is provided with piezo resistance layers. The motion of the beams due to the action of acceleration is converted into electrical signals. The resonant frequency of the beams of the accelerometer chip is above the resonant frequency of the casing itself, so that the acceleration components above this resonant frequency are damped by the casing and therefore most acceleration components in the resonant frequency of the beam are damped. As a result, the beams of the accelerometer chip can be protected from the impacts due to the dropping of the accelerometer, or the like.Type: GrantFiled: February 18, 1994Date of Patent: April 16, 1996Assignee: Nippondenso Co., Ltd.Inventors: Toshitaka Yamada, Masahito Imai, Akira Tai