Patents by Inventor Akira Takata

Akira Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130200182
    Abstract: A process applicable to different lithologies of phosphate ore with siliceous-carbonated matrix from igneous or sedimentary origin rocks includes ore preparation by comminution through crushing, grinding, and de-sliming, prior to apatite flotation. During flotation, ground and de-slimed ore pulp with high concentration of solids, above 40%, is initially conditioned with depressant reagent, e.g., a vegetable starch gelatinized with sodium hydroxide solution, and conditioning with collector reagent (sulphosuccinate or sulphosuccinamate). This conditioned pulp floats apatite in a circuit with rougher, scavenger, cleaner and recleaner flotation steps. CO2 gas can be added in all or some flotation steps to a bubble generation system.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 8, 2013
    Inventors: Sebastião Eduardo De Rezende, Josiane Silvia Martins, Elves Matiolo, Lauro Akira Takata
  • Publication number: 20120087850
    Abstract: The present invention, named Bunge/Fosfertil process, is applicable at different lithologies of phosphate ore with carbonated-silica matrix from igneous and sedimentary sources, i.e., consists of comminutioning the ore by crushing, homogenization, milling and disliming, prior to the apatite flotation. The dislimed and milled ore pulp with solids concentration above 40%, being initialy conditioned with a depressor reactant, a vegetable source polymer gelled with sodium hydroxide solution; and subsequently, submitted to a conditioning with a scavenger reactant of the sulphosuccinate or sulphosuccinamate groups. This pulp conditioned with reactants goes to the apatite flotation in a circuit comprising the “rougher”, “scavenger”, “cleaner” and “recleaner” steps. In all steps of the circuit flotation the carbon dioxide gas may be added up to saturation of such gas in the temperature and pressure conditions of the pulp.
    Type: Application
    Filed: June 9, 2010
    Publication date: April 12, 2012
    Inventors: Sebastião Eduardo De Rezende, Josiane Silvia Martins, Elves Matiolo, Lauro Akira Takata
  • Patent number: 6677214
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: January 13, 2004
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6379252
    Abstract: The present invention relates to a game program rewrite system for supplying data of a game program of a plurality of terminal stations from a host station and writing the data in portable information storage media applied to game execution units in the terminal stations in response to requests, and a program rewrite system suitable for this game program supply system, and aims at enabling construction of a game-on-demand system including a number of terminal stations with no excess of requirement to equipment of a network or the data throughput of the host station. In order to attain the above object, a host station (1) supplies data of a game program to a terminal station (2) online through a communication network. The data of the game program is supplied to the terminal station (2) offline too. The data of the game program preserved in the terminal station (2) is written in a game execution storage medium (20) in response to a request of a user.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: April 30, 2002
    Assignee: Mega Chips Corporation
    Inventors: Akira Takata, Takahiro Masuda, Toshihiro Satou, Tetsuji Kajitani, Masashi Kuramoto
  • Publication number: 20010003714
    Abstract: The present invention relates to a game program rewrite system for supplying data of a game program of a plurality of terminal stations from a host station and writing the data in portable information storage media applied to game execution units in the terminal stations in response to requests, and a program rewrite system suitable for this game program supply system, and aims at enabling construction of a game-on-demand system including a number of terminal stations with no excess of requirement to equipment of a network or the data throughput of the host station.
    Type: Application
    Filed: November 28, 1997
    Publication date: June 14, 2001
    Inventors: AKIRA TAKATA, TAKAHIRO MASUDA, TOSHIHIRO SATOU, TETSUJI KAJITANI, MASASHI KURAMOTO
  • Patent number: 6225668
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: May 1, 2001
    Assignees: Mega Chips Corporation, Silicon Technology Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6177706
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atoms currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anistropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: January 23, 2001
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6137120
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: October 24, 2000
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6106734
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diaphragm which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: August 22, 2000
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6025252
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: February 15, 2000
    Assignee: Mega Chips Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 5895887
    Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, power supply pins and ground pins are provided on opposite edges of a package with input address pins being arranged therebetween and output data pins being arranged outside the same. Control pins and a nonconnected excess pin are arranged in the center. This allows the package to omit wires and reduce chip size.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: April 20, 1999
    Assignees: Mega Chips Corporation, Tom Dang-hsing Yiu
    Inventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
  • Patent number: 5866940
    Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: February 2, 1999
    Assignees: Mega Chips Corporation, Tom Dang-hsing Yiu
    Inventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
  • Patent number: 5847449
    Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: December 8, 1998
    Assignees: Mega Chips Corporation, Tom Dang-hsing Yiu
    Inventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
  • Patent number: 5825083
    Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: October 20, 1998
    Assignees: Mega Chips Corporation, Tom Dang-hsing Yiu
    Inventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
  • Patent number: 5753553
    Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: May 19, 1998
    Assignee: Mega Chips Corporation
    Inventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
  • Patent number: 5738731
    Abstract: A solar cell comprising:a first junction part having a first conductivity type first semiconductor film and a second conductivity type second semiconductor film formed on an upper surface of said first semiconductor film; anda second junction part having a first conductivity type third semiconductor film formed on an upper surface of said second semiconductor film and a second conductivity type fourth semiconductor formed on an upper surface of said third semiconductor film,said junction parts arranged from that having a larger forbidden band width along the direction of progress of light through said semiconductor layers,said first, second, third, and fourth semiconductor films being formed of single-crystalline filming;wherein an interlayer conductor prepared from a metal forming ohmic junctions with each of said junction parts and having a thickness capable of transmitting light therethrough is interposed between said first and second junction parts; andwherein said second semiconductor film arranged on on
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: April 14, 1998
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 5700975
    Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: December 23, 1997
    Assignees: Mega Chips Corporation, Tom Dang-hsing Yiu
    Inventors: Akira Takata, Tetsuo Hikawa, Takashi Sawada, Tom Dang-hsing Yiu, Ful-Long Ni
  • Patent number: 5666304
    Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: September 9, 1997
    Assignee: Mega Chips Corporation
    Inventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada
  • Patent number: 5650959
    Abstract: This memory device includes a plurality of word lines, a plurality of bit lines, a plurality of virtual ground lines, memory cells arranged at the intersections between the word and bit lines, a potential setting unit for setting the potential of the virtual ground lines to a ground or bias level, and a sense amplifier for detecting storage information of a target memory cell through the bit line when the virtual ground line connected to the target memory cell is set to the ground level by the potential setting unit. To read out information from a memory cell Mij, a virtual ground line GLi connected to the electrode of this memory cell is set to the ground level, and the remaining virtual ground lines are connected to a common bias potential line set to the bias level.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: July 22, 1997
    Assignee: NKK Corporation
    Inventors: Tetsuya Hayashi, Akira Takata, Kazuhiro Watanabe
  • Patent number: 5640367
    Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming a plurality of types of memory cells having different electrical properties. Thus, storage data per memory cell is so multivalued that the number of memory cells is reduced.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: June 17, 1997
    Assignee: Mega Chips Corporation
    Inventors: Tetsuo Hikawa, Akira Takata, Takashi Sawada