Abstract: A bus switching circuit includes a bus switching element which is connected between a first input/output terminal and a second input/output terminal, a first switching element which is connected between the second input/output terminal and a first voltage wiring, and a second switching element which is connected between the second input/output terminal and the first voltage wiring, the second switching element having an internal resistance to an electric current flowing therethrough which is larger than that of the first switching element. The bus switching circuit further includes a signal generation circuit which controls the first switching element and the second switching element by outputting the first control signal and the second control signal based on a result of the comparison between a first voltage applied to the first input/output terminal and a first threshold value.

Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A bus switch circuit according to an embodiment includes a signal transmission circuit connected between a first terminal and a second terminal. The bus switch circuit includes a first switch element controlled by a first control signal. The bus switch circuit includes a second switch element controlled by a second control signal. The bus switch circuit includes a delay signal generating circuit that outputs a delay signal based on a first signal varying with a first voltage applied to the first terminal and a second signal varying with a second voltage applied to the second terminal. The bus switch circuit includes a control signal generating circuit that outputs the first control signal and the second control signal based on the first signal, the second signal, and the delay signal.

Abstract: According to one embodiment, a level shifter includes a high-side switch and a low-side switch. The high-side switch is connected between a high-potential power supply and a connection point and turned on in accordance with an input signal. The low-side switch is connected between the connection point and a low-potential power supply and turned on in accordance with an input signal. A ratio between ON resistance of the high-side switch and ON resistance of the low-side switch is set in accordance with a signal difference between an output signal and the input signal. The output signal is outputted to the connection point.

Abstract: A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with th

Abstract: A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data signal into the data communication path, and has a buffer amplifier section for compensating the data signal.

Abstract: The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of P1 and N1 whose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P1.

Abstract: A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with th

Abstract: The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of P1 and N1 whose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P1.

Abstract: A semiconductor device of an embodiment of the invention has a package substrate, and a semiconductor chip mounted on the package substrate. The semiconductor chip has an output section, and a filter section for decreasing the electromagnetic noise generated from the data communication path. The output section outputs a data signal into the data communication path, and has a buffer amplifier section for compensating the data signal.

Abstract: The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of P1 and N1 whose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P1.

Abstract: A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer.

Abstract: An oscillation circuit comprises a ring oscillator configured to have at least an odd number of stages of inverters, and a frequency multiplier section configured to output as a multiplied output, an exclusive OR of signals taken out from the inverters at least at two stages of the ring oscillator.

Abstract: A signal level shifting bus switch is connected between a first semiconductor device driven by a first supply voltage VccA having a first difference from a reference voltage and a second semiconductor device driven by a second supply voltage VccB having a second difference, less than the first difference, from the reference voltage, and comprises a first I/O terminal for inputting/outputting the first supply voltage; a second I/O terminal for inputting/outputting the second supply voltage; and a control terminal provided to receive a control voltage.

Abstract: A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer.

Abstract: A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.