Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.

Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.

Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.

Abstract: In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.

Abstract: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided.

Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.

Abstract: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided.

Abstract: In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.

Abstract: On receiving a target address specification from a programmer, an execution code reconversion unit reconverts an operation code of an execution code loaded in the specified address to a mnemonic code. When the execution code includes a subconstant as an operand, a constant restoration unit detects constant division information that shows the subconstant included in the execution code in a debug information storage unit, in order to specify the long-word constant from which the subconstant has been generated. The constant restoration unit then replaces the subconstant with the long-word constant. As a result, the mnemonic code is displayed with the long-word constant.

Abstract: The AD conversion control section of the processor sets the clock generating circuit of the output port alternately to an L-level output condition and an H-level output condition to generate a clock signal. A chip select signal is caused to be output from the chip select circuit of the output port in synchronization with output of the first clock signal by the interruption signal. Furthermore, the bit data output in series bit by bit from the AD converter in synchronization with occurrence of a clock signal is incorporated bit by bit in synchronization with the interruption signal from the input ports to be stored in the register.

Abstract: The control unit of a computer system comprises a first storing device for holding written data while the power is on, a second storing device for holding the written data, even when the power is off and a power-off preserving device for terminating power to the system after transferring the data held in the first storing device to the second storing device. The control system can be utilized to only store the effective contents of the operating data to thereby enable data reconstruction upon resumption of power. The control device can interface with a window system processing device which can enable the refreshing of graphic display information upon resumption of power. The second storing device may have limited memory capacity and the operator can be informed of its capacity prior to a final shut-off of power. The control unit can further identify those programs that are not capable of being restored to their original condition and accordingly canceling any program execution when such a condition is judged.