Abstract: A wire bonding apparatus according to an embodiment bonds a wire to a bonding portion by generating an ultrasonic vibration in a state of pressing the wire onto the bonding portion. The wire bonding apparatus includes a bonding tool that causes the wire to contact the bonding portion and applies a load, an ultrasonic horn that generates the ultrasonic vibration, a load sensor that continuously detects the load applied from the bonding tool to the bonding portion, and a controller that controls the operation of the bonding tool and the ultrasonic horn. The controller analyzes data of the load output from the load sensor between when the wire contacts the bonding portion and when the ultrasonic vibration is generated, and controls the operation of the bonding tool and the ultrasonic horn based on an analysis result.

Abstract: According to an embodiment, a battery includes an exterior container, a lid member, a plurality of electrode groups, a first lead, a second lead, and an electrode terminal. The lid member closes an opening of an inner cavity of the exterior container, and the plurality of electrode groups are stored in the inner cavity. A first current collecting tab protruding toward the lid member in a first electrode is joined with the first lead, and a second current collecting tab protruding toward the lid member in the second electrode different from the first electrode is joined with the second lead separate from the first lead. The first and second leads are together connected to the electrode terminal exposed on an outer surface of the lid member.

Abstract: A wire bonding apparatus according to an embodiment bonds a wire to a bonding portion by generating an ultrasonic vibration in a state of pressing the wire onto the bonding portion. The wire bonding apparatus includes a bonding tool that causes the wire to contact the bonding portion and applies a load, an ultrasonic horn that generates the ultrasonic vibration, a load sensor that continuously detects the load applied from the bonding tool to the bonding portion, and a controller that controls the operation of the bonding tool and the ultrasonic horn. The controller analyzes data of the load output from the load sensor between when the wire contacts the bonding portion and when the ultrasonic vibration is generated, and controls the operation of the bonding tool and the ultrasonic horn based on an analysis result.

Abstract: A semiconductor device includes a base, a first semiconductor chip mounted on the base, and a second semiconductor chip provided above the first semiconductor chip. The second semiconductor chip includes a first portion, a second portion including a region directly above a center of the first semiconductor chip, and a third portion including part of a portion of the second semiconductor chip other than a region directly above the first semiconductor chip. The second portion is thicker than the first portion. The third portion is thicker than the second portion and is disposed at a position sandwiching the first semiconductor chip.

Abstract: A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.

Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.

Abstract: According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.

Abstract: A semiconductor device includes a base, a first semiconductor chip mounted on the base, and a second semiconductor chip provided above the first semiconductor chip. The second semiconductor chip includes a first portion, a second portion including a region directly above a center of the first semiconductor chip, and a third portion including part of a portion of the second semiconductor chip other than a region directly above the first semiconductor chip. The second portion is thicker than the first portion. The third portion is thicker than the second portion and is disposed at a position sandwiching the first semiconductor chip.

Abstract: According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.

Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.

Abstract: A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.

Abstract: According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.

Abstract: A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed.

Abstract: According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.

Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating ma

Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separate

Abstract: A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a semiconductor element, a first electrode of the semiconductor chip being configured on a first surface of the semiconductor element, a second electrode of the semiconductor element being configured on a second surface opposed to the first surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, a first hole and a second hole being configured in the encapsulating material, a portion of the first electrode and a portion of the second electrode being exposed, a first conductive material being connected to the first surface of the semiconductor chip via the first hole, a second conductive material being connected to the second surface of the semiconductor chip via the second hole, and a plating film covering five surfaces of the first conductive material other than one surface contacting with the encapsulating material and five surfaces of

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating ma