Patents by Inventor Akira Toriumi

Akira Toriumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11157805
    Abstract: A neuron circuit includes: an input terminal to which spike signals are continuously input; a first switch element that has a first end coupled to the input terminal and a second end coupled to a node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when spike signals are input within a time period; a feedback circuit coupled to the node, and causing the input terminal to be at a level when the first switch element goes into the low resistance state; and a second switch element that is connected in series with the first switch element between the input terminal and the node, remains in a low resistance state even when spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the level.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 26, 2021
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takeaki Yajima, Akira Toriumi
  • Patent number: 10748776
    Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 18, 2020
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Publication number: 20190378002
    Abstract: A neuron circuit includes: an input terminal to which spike signals are continuously input; a first switch element that has a first end coupled to the input terminal and a second end coupled to a node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when spike signals are input within a time period; a feedback circuit coupled to the node, and causing the input terminal to be at a level when the first switch element goes into the low resistance state; and a second switch element that is connected in series with the first switch element between the input terminal and the node, remains in a low resistance state even when spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the level.
    Type: Application
    Filed: July 18, 2017
    Publication date: December 12, 2019
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takeaki Yajima, Akira Toriumi
  • Publication number: 20190228978
    Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.
    Type: Application
    Filed: February 23, 2017
    Publication date: July 25, 2019
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20170317170
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Application
    Filed: November 2, 2015
    Publication date: November 2, 2017
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Patent number: 9722026
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 1, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Toshiyuki Tabata, Choong Hyun Lee, Tomonori Nishimura, Cimang Lu
  • Patent number: 9691620
    Abstract: A semiconductor structure includes: a germanium layer 30; and an insulating film that has a film 32 that includes a germanium oxide and is formed on the germanium layer and a high dielectric oxide film 34 that is formed on the film including the germanium oxide and has a dielectric constant higher than that of a silicon oxide, wherein: an EOT of the insulating film is 2 nm or less; and on a presumption that an Au acting as a metal film is formed on the insulating film, a leak current density is 10?5×EOT+4 A/cm2 or less in a case where a voltage of the metal film with respect to the germanium layer is applied from a flat band voltage to an accumulation region side by 1 V.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: June 27, 2017
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee
  • Patent number: 9647074
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 9, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20160276445
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 22, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Publication number: 20160218182
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Application
    Filed: June 6, 2014
    Publication date: July 28, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Toshiyuki TABATA, Choong Hyun LEE, Tomonori NISHIMURA, Cimang LU
  • Patent number: 9306026
    Abstract: A semiconductor structure includes: a germanium layer 30; and an aluminum oxynitride film 32 that is formed on the germanium layer, wherein: an EOT of the aluminum oxynitride film is 2 nm or less; Cit/Cacc is 0.4 or less; on a presumption that Au acting as a metal film is formed on the aluminum oxynitride film, the Cit is a capacitance value between the germanium layer and the metal film at a frequency of 1 MHz in a case where a voltage of the metal film with respect to the germanium layer is applied to an inversion region side by 0.5 V; and the Cacc is a capacitance value between the germanium layer and the metal film in an accumulation region.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 5, 2016
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Toshiyuki Tabata
  • Publication number: 20150228492
    Abstract: A semiconductor structure includes: a germanium layer 30; and an insulating film that has a film 32 that includes a germanium oxide and is formed on the germanium layer and a high dielectric oxide film 34 that is formed on the film including the germanium oxide and has a dielectric constant higher than that of a silicon oxide, wherein: an EOT of the insulating film is 2 nm or less; and on a presumption that an Au acting as a metal film is formed on the insulating film, a leak current density is 10?5×EOT+4 A/cm2 or less in a case where a voltage of the metal film with respect to the germanium layer is applied from a flat band voltage to an accumulation region side by 1 V.
    Type: Application
    Filed: April 18, 2013
    Publication date: August 13, 2015
    Inventors: Akira Toriumi, Choong-hyun Lee
  • Publication number: 20150171185
    Abstract: A semiconductor structure includes: a germanium layer 30; and an aluminum oxynitride film 32 that is formed on the germanium layer, wherein: an EOT of the aluminum oxynitride film is 2 nm or less; Cit/Cacc is 0.4 or less; on a presumption that Au acting as a metal film is formed on the aluminum oxynitride film, the Cit is a capacitance value between the germanium layer and the metal film at a frequency of 1 MHz in a case where a voltage of the metal film with respect to the germanium layer is applied to an inversion region side by 0.5 V; and the Cacc is a capacitance value between the germanium layer and the metal film in an accumulation region.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Akira Toriumi, Toshiyuki Tabata
  • Patent number: 8063452
    Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVA) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVB); and M?xOy, where M? is a second metal species selected from the group 3 (IIIB) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 22, 2011
    Assignee: The University of Tokyo
    Inventors: Akira Toriumi, Koji Kita, Kazuyuki Tomida, Yoshiki Yamamoto
  • Publication number: 20100176478
    Abstract: Provided are a novel method and a novel structure for bringing a Ge or SiGe compound and a metal into ohmic contact with each other. A semiconductor device is provided with a portion composed of only i) Ge or SiGe compound, ii) a metal, and iii) an insulator or a semiconductor arranged between the material i) and the metal ii). In the semiconductor device, A) the material i) and the metal ii) have Schottky junction in the case where the holes of the material i) are majority carriers, and/or B) the material i) and the metal ii) are in an ohmic contact when the electrons of the material i) are majority carriers.
    Type: Application
    Filed: September 1, 2008
    Publication date: July 15, 2010
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Patent number: 7671426
    Abstract: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: March 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Mise, Akira Toriumi
  • Publication number: 20100019357
    Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVA); and M?xOy, where M? is a second metal species selected from the group 3 (IIIA) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.
    Type: Application
    Filed: August 30, 2005
    Publication date: January 28, 2010
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Akira Toriumi, Koji Kita, Kazuyuki Tomida, Yoshiki Yamamoto
  • Publication number: 20090173998
    Abstract: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.
    Type: Application
    Filed: February 10, 2009
    Publication date: July 9, 2009
    Inventors: Nobuyuki Mise, Akira Toriumi
  • Patent number: 7507632
    Abstract: In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyuki Mise, Akira Toriumi