Abstract: A display device includes a display panel in which a display screen and an indicator region are two-dimensionally arranged, an indicator substrate which is mounted with a light source component and which is arranged on a back face side of the display panel so as to face the indicator region but not to face the display screen, and a control substrate which is a separate part from the indicator substrate and on which a control circuit for the display screen is formed. The control substrate is arranged on the back face side of the display panel and arranged distant from the display panel than the indicator substrate, and the control substrate is arranged so as not to face at least a portion of each of the display screen and the indicator substrate.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: The present invention relates to a float-glass manufacturing apparatus including a float bath and a heat treatment furnace, in which the heat treatment furnace includes: a dross box including a plurality of lift-out rolls; an annealing furnace including a plurality of lehr rolls; a first partitioning part; a second partitioning part; a gas ejection nozzle; and a guide member.

Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.

Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Abstract: A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

Abstract: A change-over switch includes a swing member configured to swing in response to an operation from the outside, a contact member configured to swing about the swing axis identical to the axis of the swing member and including a plurality of movable contacts extending in different directions, and a substrate on which a fixed contact is formed, the fixed contact configured to contact the plurality of movable contacts of the contact member. In the change-over switch, the movable contact that contacts the fixed contact formed on the substrate is changed over by swinging of the contact member in conjunction with swinging of the swing member. A switch device includes a power source switch configured to open and close a circuit which supplies electric power to a power load, and a change-over switch configured to change over electric power supplied to the power load.

Abstract: An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

Abstract: A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

Abstract: The present invention relates to a float-glass manufacturing apparatus including a float bath and a heat treatment furnace, in which the heat treatment furnace includes: a dross box including a plurality of lift-out rolls; an annealing furnace including a plurality of lehr rolls; a first partitioning part; a second partitioning part; a gas ejection nozzle; and a guide member.

Abstract: A change-over switch includes a swing member configured to swing in response to an operation from the outside, a contact member configured to swing about the swing axis identical to the axis of the swing member and including a plurality of movable contacts extending in different directions, and a substrate on which a fixed contact is formed, the fixed contact configured to contact the plurality of movable contacts of the contact member. In the change-over switch, the movable contact that contacts the fixed contact formed on the substrate is changed over by swinging of the contact member in conjunction with swinging of the swing member. A switch device includes a power source switch configured to open and close a circuit which supplies electric power to a power load, and a change-over switch configured to change over electric power supplied to the power load.

Abstract: A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.

Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.

Abstract: Provided is a processing apparatus where the exchange of an operating program for an apparatus body is not required each time a jig unit is exchanged. The processing apparatus includes an apparatus body and a jig unit. A master control device is mounted on the jig unit. Operations of the jig unit and the apparatus body are controlled by an operating program in the master control device.

Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that perform predetermined processing on input data; an input/output module that operates as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that changes a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that performs a pipeline processing by each of the processing modules constituting the pipeline.

Abstract: Motion vector calculator sets motion vector of block corresponding to partial area of first image based on the block and similarity between the block and partial area of second image, motion vector reliability calculator calculates reliability of the motion vector based on distribution of the similarities, motion vector corrector corrects motion vector of low-reliability block having reliability lower than predetermined reliability based on motion vector of high-reliability block different from the low-reliability block and having reliability equal to or higher than the predetermined reliability, and image processor sets second pixel of the second image and corresponds to first pixel of the first image based on the motion vector corrected by the motion vector corrector, and performs image processing using signal value of the first pixel and signal value of the second pixel.

Abstract: A memory access device for controlling accesses to a memory having a plurality of banks by a plurality of processing blocks including at least one high-priority processing block, connected to a common data bus, and outputting access requests for requesting access to the memory has a memory controller connected to the data bus to control access to the connected memory in response to the access requests while outputting operation information of the memory; and an access selection unit configured to change a designation sequence of the banks according to the operation information at the time when the high-priority processing block continuously accesses the plurality of banks and output the access requests in the changed sequence, wherein the access selection unit is configured to further change the designation sequence according to the changing operation information during a period while the access requests are not accepted by the memory controller.