Patents by Inventor Akira YABU

Akira YABU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with pin register to set input/output direction and bitwidth of data signals
    Patent number: 9030895
    Abstract: A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Miura, Yoshinori Haraguchi, Kazuhiko Abe, Shoji Kaneko, Akira Yabu
  • INFORMATION PROCESSING SYSTEM AND SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20100030954
    Abstract: A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Seiji MIURA, Yoshinori HARAGUCHI, Kazuhiko ABE, Shoji KANEKO, Akira YABU
  • MEMORY MODULE, MEMORY SYSTEM, AND DATA PROCESSING SYSTEM
    Publication number: 20070271409
    Abstract: A user-friendly data processing system apparatus which ensures the expandability of memory capacity and high speed processing with low cost is provided. The data processing system is composed of a data processing unit, a volatile memory and a nonvolatile memory. The data processing unit, the volatile memory and the nonvolatile memory are connected in series and by reducing the number of connection signals fast processing is realized while maintaining the memory capacity expandability. Upon transferring a data of the nonvolatile memory to the volatile memory, an error correction is executed, therefore, the reliability is improved. The data processing system composed of the plurality of memory chips is formed as a data processing system module in which the each chips are stacked and arranged, and wiring is formed by ball grid array (BGA) and bonding between the chips.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 22, 2007
    Inventors: Seiji Miura, Akira Yabu, Yoshinori Haraguchi