Patents by Inventor Akira Yabushita
Akira Yabushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110175634Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
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Publication number: 20110136272Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: February 1, 2011Publication date: June 9, 2011Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
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Patent number: 7901958Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: GrantFiled: August 10, 2010Date of Patent: March 8, 2011Assignee: Renesas Electronics CorporationInventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
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Publication number: 20110014727Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.Type: ApplicationFiled: September 16, 2010Publication date: January 20, 2011Inventors: Akira YABUSHITA, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
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Publication number: 20100304510Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: August 10, 2010Publication date: December 2, 2010Inventors: Masayoshi OKAMOTO, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
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Publication number: 20100301884Abstract: A semiconductor chip inspection apparatus largely reduces occurrence of damage due to foreign matter in an inspection process and improves durability at the same time of miniaturization is provided. As to a highly accurate thin-film probe sheet which performs: a contact to electrode pads arranged at a narrow pitch and a high density along with integration of semiconductor chip; and an inspection of semiconductor chips, by providing two layers of metal films selectively removable in a step-like shape in a periphery region of fine contact terminal having sharp tips and arranged at a high density and a narrow pitch at the same level as electrode pads, an upper periphery of the contact terminals is covered with an insulating film, and a large space region is formed.Type: ApplicationFiled: May 26, 2010Publication date: December 2, 2010Inventors: Etsuko Takane, Yasunori Narizuka, Akira Yabushita, Kenji Kawakami, Akio Hasebe
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Patent number: 7351597Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: GrantFiled: May 18, 2007Date of Patent: April 1, 2008Assignee: Renesas Technology Corp.Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Publication number: 20080020498Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: September 25, 2007Publication date: January 24, 2008Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
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Publication number: 20070218572Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: ApplicationFiled: May 18, 2007Publication date: September 20, 2007Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Patent number: 7219422Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: GrantFiled: January 29, 2004Date of Patent: May 22, 2007Assignee: Renesas Technology Corp.Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Publication number: 20060094162Abstract: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.Type: ApplicationFiled: October 20, 2005Publication date: May 4, 2006Inventors: Akira Yabushita, Yasunori Narizuka, Susumu Kasukabe, Terutaka Mori, Etsuko Takane, Akio Hasebe, Kenji Kawakami
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Publication number: 20060043593Abstract: In the connecting apparatus for inspecting the semiconductor chip, in which contact terminals are electrically connected to each of the plurality of electrode pads formed on the semiconductor chips, a part of metal projections in the shape of quadrangular pyramid which constitute the contact terminals is composed of insulator in the present invention. Therefore, the inspection of semiconductor chips performed by simultaneously transmitting high-speed signals to the plurality of minute electrode pads arranged at a narrow pitch on the semiconductor chips can be realized.Type: ApplicationFiled: July 20, 2005Publication date: March 2, 2006Inventors: Terutaka Mori, Yasunori Narizuka, Akira Yabushita, Etsuko Takane, Akio Hasebe, Kenji Kawakami
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Publication number: 20050093565Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: October 20, 2004Publication date: May 5, 2005Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
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Publication number: 20040183556Abstract: Provided is a fabrication method of a semiconductor integrated circuit device which comprises forming a pushing mechanism by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal, placing an elastomer in the groove so that a predetermined amount exceeds the groove, and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. The present invention makes it possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Inventors: Yuji Wada, Susumu Kasukabe, Takehiko Hasebe, Yasunori Narizuka, Akira Yabushita, Terutaka Mori, Akio Hasebe, Yasuhiro Motoyama, Teruo Shoji, Masakazu Sueyoshi
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Patent number: 6652342Abstract: A gas discharge type display apparatus includes a front substrate having a plurality of first electrodes and a back substrate having a plurality of second electrodes and at least ones of the first and second electrodes are made of the photosensitive material containing silver exposed by using the laser thereby, making a mask unnecessary.Type: GrantFiled: April 27, 1999Date of Patent: November 25, 2003Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Michifumi Kawai, Ryohei Satoh, Shigeaki Suzuki, Akira Yabushita, Masahito Ijuin
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Patent number: 6624575Abstract: A gas discharge display device having a first substrate, a plurality of first electrodes having a substantially rectangular form being arranged on the first substrate, a plurality of second electrodes, respective ones of the plurality of second electrodes being formed on respective ones of the plurality of first electrodes, and each of the plurality of second electrodes having an extension extending beyond an end of a respective one of the plurality of first electrodes on which respective ones of the plurality of second electrodes are formed and in an oblique direction therefrom. The extension of the plurality of second electrodes extend beyond opposite ends of alternate ones of the plurality of first electrodes.Type: GrantFiled: February 4, 2002Date of Patent: September 23, 2003Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Tomohiro Murase
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Patent number: 6621217Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.Type: GrantFiled: February 11, 2002Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
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Patent number: 6429586Abstract: A method of making a gas discharge display panel and a gas discharge display device using laser processing so that the manufacturing time to form wiring on a substrate thereof is significantly reduced. In order to achieve this, the gas discharge display panel is provided with a first substrate having a plurality of first electrodes and a plurality of second electrodes, and the first electrodes are laser processed to have a substantially rectangular shape. The second electrodes are formed on the first electrodes, and a second substrate having a plurality of third electrodes which is opposed to the first substrate is provided.Type: GrantFiled: January 5, 1999Date of Patent: August 6, 2002Assignee: Hitachi, Ltd.Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Tomohiro Murase
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Publication number: 20020089285Abstract: A gas discharge display device having a first substrate, a plurality of first electrodes having a substantially rectangular form being arranged on the first substrate, a plurality of second electrodes, respective ones of the plurality of second electrodes being formed on respective ones of the plurality of first electrodes, and each of the plurality of second electrodes having an extension extending beyond an end of a respective one of the plurality of first electrodes on which respective ones of the plurality of second electrodes are formed and in an oblique direction therefrom. The extension of the plurality of second electrodes extend beyond opposite ends of alternate ones of the plurality of first electrodes.Type: ApplicationFiled: February 4, 2002Publication date: July 11, 2002Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawat, Masahito Tjuin, Akira Yabushita, Tomohiro Murase
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Publication number: 20020070665Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.Type: ApplicationFiled: February 11, 2002Publication date: June 13, 2002Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase