Abstract: The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.

Abstract: The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10, implanting a dopant into a region of the polysilicon film 32 for a resistance element to be formed in, patterning the polysilicon film 32 to from the resistance element 46 of the polysilicon film 32 with the dopant inplanted in and gate electrodes 44a, 44b of the polysilicon film 32 with the dopant not implanted in. Accordingly, resistance element can be formed while suppressing influences on characteristics of the transistor formed on one and the same substrate concurrently with forming the resistance element.

Abstract: The semiconductor device comprises an insulating film 114 formed mainly of a film of polyallyl ether resin; an interconnection structure 116 buried in the insulating film 114, and having a via portion buried in a groove-shaped via hole and an interconnection portion formed on the via portion and having an eave-shaped portion horizontally extended beyond the via portion; an insulating film 118 formed on the insulating film 114 with the interconnection structure 116 buried in and formed mainly of a film of organosilicate glass; and an interconnection structure 120 buried in the insulating film 118 and connected to the interconnection structure 116. Thus, the stresses to be exerted to the insulating films are decreased, the generation of cracks and peelings generated in the interfaces between the insulating films and in the insulating films due to the stresses generated at the ends of the interconnection structures can be effective prevented.

Abstract: A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10, implanting a dopant into a region of the polysilicon film 32 for a resistance element to be formed in, patterning the polysilicon film 32 to from the resistance element 46 of the polysilicon film 32 with the dopant inplanted in and gate electrodes 44a, 44b of the polysilicon film 32 with the dopant not implanted in. Accordingly, resistance element can be formed while suppressing influences on characteristics of the transistor formed on one and the same substrate concurrently with forming the resistance element.

Abstract: The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.

Abstract: The semiconductor device comprises an insulating film 114 formed mainly of a film of polyallyl ether resin; an interconnection structure 116 buried in the insulating film 114, and having a via portion buried in a groove-shaped via hole and an interconnection portion formed on the via portion and having an eave-shaped portion horizontally extended beyond the via portion; an insulating film 118 formed on the insulating film 114 with the interconnection structure 116 buried in and formed mainly of a film of organosilicate glass; and an interconnection structure 120 buried in the insulating film 118 and connected to the interconnection structure 116. Thus, the stresses to be exerted to the insulating films are decreased, the generation of cracks and peelings generated in the interfaces between the insulating films and in the insulating films due to the stresses generated at the ends of the interconnection structures can be effective prevented.

Abstract: A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a pad conductor filled in the pad groove.

Abstract: A semiconductor device having a semiconductor substrate including semiconductor elements and an underlying wiring layer, and an underlying insulating layer covering the underlying wiring layer. Via conductors are also included and are filled in via holes extending through the underlying insulating layer and reaching the underlying wiring layer. Further, an insulating stack layer formed on the underlying insulating layer and covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern and a pad conductor filled in the pad groove.

Abstract: A semiconductor device includes a semiconductor substrate including semiconductor elements and an underlie wiring layer, an underlie insulating layer covering the underlie wiring layer; via conductors filled in via holes extending through the underlie insulating layer and reaching the underlie wiring layer, an insulating stack layer formed on the underlie insulating layer, covering the via conductors, the insulating stack layer including a first and a second insulating layer having different etching characteristic, a pad groove formed through the insulating stack layer, defining a pad region in which the via conductors are exposed, the pad region including therein at least an etching enhancing remaining insulation layer pattern; and a, pad conductor filled in the pad groove.

Abstract: A damascene wiring structure having: a lower wiring structure; an interlayer insulating film covering the lower wiring structure; a wiring trench formed in the interlayer insulating film from an upper surface thereof, and a via hole passing through the interlayer insulating film from a lower surface of the wiring trench in an inner area thereof and reaching the lower wiring structure, the via hole having a diameter smaller than a width of the wiring trench; an insulating pillar pattern projecting upward from the lower surface of the wiring trench in an area outside of the via hole, the insulating pillar pattern being made of a same material as the interlayer insulating film, wherein a first occupied area factor of the insulating pillar pattern in a first area of the wiring trench near said via hole is higher than a second occupied area factor of the insulating pillar pattern in a second area of the wiring trench remote from the via hole; and a dual damascene wiring formed by filling the wiring trench and said

Abstract: A damascene wiring structure having: a lower wiring structure; an interlayer insulating film covering the lower wiring structure; a wiring trench formed in the interlayer insulating film from an upper surface thereof, and a via hole passing through the interlayer insulating film from a lower surface of the wiring trench in an inner area thereof and reaching the lower wiring structure, the via hole having a diameter smaller than a width of the wiring trench; an insulating pillar pattern projecting upward from the lower surface of the wiring trench in an area outside of the via hole, the insulating pillar pattern being made of a same material as the interlayer insulating film, wherein a first occupied area factor of the insulating pillar pattern in a first area of the wiring trench near said via hole is higher than a second occupied area factor of the insulating pillar pattern in a second area of the wiring trench remote from the via hole; and a dual damascene wiring formed by filling the wiring trench and said