Abstract: This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

Abstract: In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

Abstract: A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.

Abstract: In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively.

Abstract: In a TIG welding process with controlled welding current pulses, DC current pulses with the frequency set at from tens to hundreds Hz (most preferably from 30 to 300 Hz) are fed to an electrode and current pulses are also fed to a filler wire so that an arc is caused to swing, whereby a large pool of molten metal can be maintained in a positive and stable manner due to the high arc pressure obtained when the welding current pulses at from tens to hundreds Hz is used.