Abstract: In analyzing a coded result to thereby calculate data distribution corresponding to a characteristic of an input image signal, rather than determining data distribution for all of the pictures, an aggregate of such pictures that have roughly the same coding difficulty is captured as one scene. This scene is prescribed as a video edit unit (VEU), so that, in configuration, the input image signal is subdivided into a plurality of video edit units (VEUs) to thereby set an average target coding rate for each of these video edit units (VEUs), which are entered as coding conditions to thereby determine data distribution for each of the pictures at the time of re-coding.

Abstract: A vibrating plate is mounted in a case, and a first coil is secured to the vibrating plate. A magnetic circuit composition is mounted in the case. The magnetic circuit composition comprises a yoke having a flange and a core formed on the flange, an annular magnet mounted on the flange of the yoke, and a top plate comprising an annular portion and a cylindrical portion projection from a peripheral portion of the annular portion. The magnetic circuit composition is resiliently supported in the case. A coil holding plate is secured to the case, and a second coil is secured to the coil holding plate. The first coil is inserted in a first magnetic gap formed in the magnetic circuit composition and the second coil is inserted in a second magnetic gap formed in the magnetic circuit composition.

Abstract: A write circuit supplies a write potential that is higher than a power supply potential to memory cells of a semiconductor memory device. The write circuit includes a reference potential generator that generates a reference potential having a substantially constant potential difference from one of a power supply potential and a ground potential. A voltage-controlled oscillator (VCO) connected to the reference potential generator receives the reference potential and generates an oscillation clock signal in proportion to the reference potential. A booster connected to the VCO generates the write potential by piling up the oscillation clock signal onto the power supply potential in a multistage manner. A write controller is connected to the booster and supplies the write potential to the memory cells in accordance with a write clock.

Abstract: To assure collective erasure irrespectively of whether or not there is any faulty sector which is an object for redundancy. A non-volatile semiconductor memory having a plurality of regions of sectors for which collective erasure of stored data can be made, comprising: a high voltage generating circuit 8 for generating a high voltage used for erasing data for the non-volatile semiconductor memory; a plurality of transistors 10A, 10B and 10C each connected between the high voltage generating circuit and the plurality of regions of sectors 9A, 9B and 9C; wherein constant current operation for the plurality of transistors 10A, 10B and 10C is performed for collective erasure of the data so as to limit the current flowing through the plurality of regions of sectors.

Abstract: A pair of reference cells 77 and 78 has the same structure as that of memory cells 51 and 52 and is arranged in the same direction on a semiconductor substrate. The memory cell 51 and the reference cell 77 (even cell) are coincident in their source/drain direction. The memory cell 52 and the reference cell 78 (odd cell) are coincident in their source/drain direction. A selection circuit 79 selects the reference cell 77 when the memory cell 51 is selected, whereas the selection circuit 79 selects the reference cell 78 when the memory cell 52 is selected. In this configuration, a semiconductor memory device is provided which can prevent erroneous read and provide stable read-out characteristic irrespectively of a change in a manufacturing process.

Abstract: A write circuit supplies a write potential that is higher than a power supply potential to memory cells of a semiconductor memory device. The write circuit includes a reference potential generator that generates a reference potential having a substantially constant potential difference from one of a power supply potential and a ground potential. A voltage-controlled oscillator (VCO) connected to the reference potential generator receives the reference potential and generates an oscillation clock signal in proportion to the reference potential. A booster connected to the VCO generates the write potential by piling up the oscillation clock signal onto the power supply potential in a multistage manner. A write controller is connected to the booster and supplies the write potential to the memory cells in accordance with a write clock.

Abstract: A nonvolatile memory increases the number of times that data can be written and the length of time that data can be stored through use of architectural and addressing features. A principal feature lies in setting as a high reliability region a specific memory sector (first sector) among a plurality of memory sectors. Within the high reliability sector, two or more memory cells are written with the same data. During reading, the simultaneously written memory cells are read simultaneously, increasing current flow through the parallel current paths. This nonvolatile memory allows the size of the high reliability sector to be adjusted using signals supplied from external to the nonvolatile memory.

Abstract: A first bit line BLa0 and a second bit line BLb0 are arranged for a single bit line BL0. A memory cell array is divided into a plurality of memory cell array blocks. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. On the further outsides arranged are an electrode wiring 20 for applying a predetermined potential ARGBD and electrode wirings 21 and 22 for applying the control signals DCBLa and DCBLb. A plurality of units, each including the memory cell array block, the control transistors and control signals, are arranged. Main bit lines each passing through these units are extended so that they are connected to the select transistors of each unit pattern. In such a configuration, the capacitive load of bit lines owing to high integration of a non-volatile semiconductor memory is reduced, thereby realizing the high speed operation of the memory.

Abstract: A memory cell array 11 is divided into plural blocks in such a manner that a first and a second split bit line BLa and BLb0 are provided for a single main bit BL0. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. Further, on both sides of the memory cell array, a wiring 20 at a predetermined potential ARGND and wirings 21 and 22 for select control signals DCBLa and DCBLb are arranged. A second gate electrode wiring 23 connects the gate of the first select transistor Q0, that of the second discharge transistor (corresponding to Q3) relative to the adjacent main bit line and the wiring 21. A first gate electrode wiring 25 connects the gate of the second select transistor Q1, that of the first discharge transistor Q2 and the wiring 21.

Abstract: A nonvolatile memory increases the number of times that data can be written and the length of time that data can be stored. A feature of the memory sets as a high reliability region a specific memory sector (for example, "0000" to "00FF") among a plurality of memory sectors. Within the high reliability sector, two or more memory cells are simultaneously written with the same data. During reading, the simultaneously written memory cells are read simultaneously, increasing current flow through the parallel current paths.

Abstract: A recording apparatus for recording compressed video data has compressed video data generator for generating a compressed video data having a plurality of intra frames each of which has no cross-reference to any other frames, and bidirectional interpolated frames and predictive frames each of which has cross-reference to other frame. In the first cycle operation, address detector detects addresses of the intra frames and stores the detected addresses in a memory. A scan information generator generates, with reference to the stored addresses in the memory, scan information for an independent frame including one or two addresses of advanced intra frames and one or two addresses of previous intra frames. The scan information is inserted to each frame and then recorded on a disk. During the reproduce of the disk, the scan information is detected to have a quick access to the intra frame located near by.

Abstract: A recording apparatus for recording a compressed video signal on a disc has an adder for adding the sequence header at the beginning of the corresponding sequence, and also adding a copy of the sequence header at a beginning of the final GOP in the corresponding sequence. The reproducing apparatus for reproducing the compressed video signal from a disc has a control for controlling the pick-up device such that under the fast reverse play mode, the pick-up device jumps backward over a copied sequence header when the pick-up device enters a new sequence from a rear end thereof, and reads the copied sequence header. Thus, the compressed video signal in the sequence can be reproduced without reading the sequence header provided at the beginning of the sequence.

Abstract: A DRAM row or column decoder having a fused stage for disabling defective rows or columns. A fuse is placed within a stage preceding the final output stage of a multi-stage row or column decoder. Because the fuse is not placed within the output stage, it is not necessary to have one fuse for each individual row or column; a single fuse can disable several decoder outputs, and thus several rows or columns can be disabled at the same time.

Abstract: A method and apparatus for precharging DRAM bit lines and data buses from the same voltage source, eliminating a separate bit line precharge source and the bit line precharge conduction paths. The precharge source for the data buses is coupled to the data buses and at the same time access transistors normally used to couple the bit line logic voltage to the data buses are enabled, in order to cause coupling of the precharge voltage source through the data buses and the access transistors to the bit lines during a precharge interval. This both precharges and equalizes the voltage on both complementary data buses and both complementary bit lines.