Patents by Inventor Akira Yoshinaka

Akira Yoshinaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4116719
    Abstract: In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.
    Type: Grant
    Filed: February 8, 1977
    Date of Patent: September 26, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hirofumi Shimizu, Akira Yoshinaka, Yoshimitsu Sugita
  • Patent number: 4016006
    Abstract: In a method of heat-treating a number of wafers each of which consists of a substance of poor heat conduction and a semiconductor layer formed on one surface of the substance, a method of heat treatment of wafers characterized in that the heat treatment is carried out under the state under which an auxiliary wafer made of a substance of good heat conduction is held in proximity to the other surface of the substance of poor heat conduction, whereby the wafers for the heat treatment are prevented from being cracked and have the characteristics made uniform.
    Type: Grant
    Filed: March 16, 1976
    Date of Patent: April 5, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yoshinaka, Takaaki Aoshima, Yoshimitsu Sugita