Patents by Inventor Akito Hara

Akito Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10857520
    Abstract: An exhaust gas-purifying three-way catalyst containing: (i) base material particles of a Nd-solid dissolved zirconia-based complex oxide comprising Nd and Zr as constituent metal elements in the following mass proportions: ZrO2 50 to 75% by mass; and Nd2O3 25 to 50% by mass, in terms of oxides; and (ii) Pd catalyst particles supported on the base material particles, wherein the Nd-solid dissolved zirconia-based complex oxide further contains at least one or more rare earth elements selected from the group consisting of yttrium, scandium, lanthanum, and praseodymium, as a constituent metal element, in an amount of a total of more than 0% by mass to 20% by mass or less in terms of an oxide.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: December 8, 2020
    Assignee: N.E. CHEMCAT CORPORATION
    Inventors: Yoshinori Takahashi, Akito Takayama, Hiroyuki Hara
  • Publication number: 20190275500
    Abstract: There are provided an exhaust gas-purifying three-way catalyst having a large palladium surface area and excellent in heat resistance and three-way purification performance, easy to produce, and also excellent in productivity, and a method for producing the same, an exhaust gas-purifying catalytic converter, and the like.
    Type: Application
    Filed: October 24, 2017
    Publication date: September 12, 2019
    Applicant: N.E. CHEMCAT CORPORATION
    Inventors: Yoshinori TAKAHASHI, Akito TAKAYAMA, Hiroyuki HARA
  • Patent number: 8264012
    Abstract: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm?3 to 5.0×1019 cm?3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018 cm?3 to 5.0×1019 cm?3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Akito Hara
  • Publication number: 20110031540
    Abstract: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm?3 to 5.0×1019 cm?3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018 cm?3 to 5.0×1019 cm?3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.
    Type: Application
    Filed: October 20, 2010
    Publication date: February 10, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Akito Hara
  • Patent number: 7847321
    Abstract: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm?3 to 5.0×1019 cm?3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018 cm?3 to 5.0×1019 cm?3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: December 7, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Akito Hara
  • Patent number: 7795619
    Abstract: A method for manufacturing a semiconductor device, including the steps of: forming a shielding film 38 on a first insulating film 37; sequentially forming a second insulating film 39 and an amorphous semiconductor film 40 on the shielding film 38; melting the amorphous semiconductor film 40 at least in portions to be channels of thin-film transistors by irradiating an energy beam onto the amorphous semiconductor film 40, and converting the amorphous semiconductor film 40 into a polycrystalline semiconductor film 41; sequentially forming a gate insulating film 43a and a gate electrode 44a on the polycrystalline semiconductor film 41 on the channels; and forming source and drain regions 41a in the polycrystalline semiconductor film 41 on sides of the gate electrode 44a, and forming a TFT 60 by use of the source and drain regions 41a, the gate insulating film 43a, and the gate electrode 44a.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Akito Hara
  • Publication number: 20080185667
    Abstract: An Mo film (6) is formed on a SiO2 film (5) by particularly using the film thickness and the deposition temperature (ambient temperature in a sputtering chamber) as the primary parameters and adjusting the film thickness to be within the range from 100 nm to 500 nm (more preferably 100 nm to 300 nm) and the deposition temperature to be within the range from 25° C. to 300° C., so as to control residual stress to have a predetermined value of 300 MPa or greater and to be oriented to increase the in-plane lattice constant. There can be thus provided a reliable CMOSTFT in which desired strain is easily and reliably imparted to polysilicon thin films (4a and 4b) to improve the mobility therein without adding an extra step of imparting the strain to the silicon thin film.
    Type: Application
    Filed: September 17, 2004
    Publication date: August 7, 2008
    Inventors: Kenichi Yoshino, Akito Hara, Michiko Takei, Takuya Hirano
  • Patent number: 7262431
    Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: August 28, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akito Hara, Nobuo Sasaki
  • Publication number: 20070085169
    Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.
    Type: Application
    Filed: December 6, 2006
    Publication date: April 19, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akito Hara, Nobuo Sasaki
  • Publication number: 20060202234
    Abstract: A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm?3 to 5.0×1019 cm?3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018 cm?3 to 5.0×1019 cm?3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.
    Type: Application
    Filed: February 27, 2006
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Publication number: 20060202233
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer having a channel region, a strain generating layer to cause strain in the channel region by applying a stress to the channel region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity region containing nitrogen, oxygen, or boron as impurities is provided in the semiconductor layer or the strain generating layer.
    Type: Application
    Filed: June 28, 2005
    Publication date: September 14, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Publication number: 20060170046
    Abstract: A method for manufacturing a semiconductor device, including the steps of: forming a shielding film 38 on a first insulating film 37; sequentially forming a second insulating film 39 and an amorphous semiconductor film 40 on the shielding film 38; melting the amorphous semiconductor film 40 at least in portions to be channels of thin-film transistors by irradiating an energy beam onto the amorphous semiconductor film 40, and converting the amorphous semiconductor film 40 into a polycrystalline semiconductor film 41; sequentially forming a gate insulating film 43a and a gate electrode 44a on the polycrystalline semiconductor film 41 on the channels; and forming source and drain regions 41a in the polycrystalline semiconductor film 41 on sides of the gate electrode 44a, and forming a TFT 60 by use of the source and drain regions 41a, the gate insulating film 43a, and the gate electrode 44a.
    Type: Application
    Filed: May 27, 2005
    Publication date: August 3, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Publication number: 20050236692
    Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.
    Type: Application
    Filed: June 28, 2005
    Publication date: October 27, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Akito Hara, Nobuo Sasaki
  • Patent number: 6927419
    Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: August 9, 2005
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Nobuo Sasaki
  • Patent number: 6909118
    Abstract: A TFT capable of showing a large gm (large ON-current) and having characteristics comparable to those of Si-MOSFET despite of its relatively simple configuration was fabricated by the steps of coating, for example, a positive photo-resist on an Mo film; subjecting the photo-resist to back light exposure from the glass-substrate side under masking with a bottom gate electrode, to thereby form a resist pattern having the same geometry and being aligned with the bottom gate electrode because exposure light is intercepted by the bottom gate electrode but can travel through the Mo film; and etching the Mo film under masking by the resist pattern to thereby form a top gate electrode in conformity with the geometry of the resist pattern in a self-aligned manner.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: June 21, 2005
    Assignee: Fujitsu Limited
    Inventor: Akito Hara
  • Patent number: 6861328
    Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: March 1, 2005
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki
  • Patent number: 6821343
    Abstract: A semiconductor manufacturing apparatus emits an energy beam for crystallizing a semiconductor film formed on a substrate. The apparatus can output a plurality of energy beams continuously in relation to time and move the energy beams to scan a target to be irradiated. The output instability of the energy beam is smaller than ±1%/h. The noise (optical noise) indicating the instability of the energy beam can be not more than 0.1 rms %.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: November 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki
  • Publication number: 20040183130
    Abstract: A TFT capable of showing a large gm (large ON-current) and having characteristics comparable to those of Si-MOSFET despite of its relatively simple configuration was fabricated by the steps of coating, for example, a positive photo-resist on an Mo film; subjecting the photo-resist to back light exposure from the glass-substrate side under masking with a bottom gate electrode, to thereby form a resist pattern having the same geometry and being aligned with the bottom gate electrode because exposure light is intercepted by the bottom gate electrode but can travel through the Mo film; and etching the Mo film under masking by the resist pattern to thereby form a top gate electrode in conformity with the geometry of the resist pattern in a self-aligned manner.
    Type: Application
    Filed: March 2, 2004
    Publication date: September 23, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Akito Hara
  • Patent number: 6767773
    Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: July 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasuyuki Sano, Akito Hara, Michiko Takei, Nobuo Sasaki
  • Patent number: 6737672
    Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 18, 2004
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki