Patents by Inventor Akito Kuramata

Akito Kuramata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194560
    Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Masaru TAKIZAWA, Akito KURAMATA
  • Publication number: 20200168460
    Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.
    Type: Application
    Filed: July 9, 2018
    Publication date: May 28, 2020
    Applicants: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Communications Technology
    Inventors: Akito KURAMATA, Shinya WATANABE, Kohei SASAKI, Kuniaki YAGI, Naoki HATTA, Masataka HIGASHIWAKI, Keita KONISHI
  • Patent number: 10600874
    Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 24, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Patent number: 10230007
    Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: March 12, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Akito Kuramata, Masataka Higashiwaki
  • Publication number: 20180033907
    Abstract: A nitride semiconductor template includes a Ga2O3 substrate, a buffer layer formed on the Ga2O3 substrate and including AlN as a principal component, a first nitride semiconductor layer formed on the buffer layer and including AlxGa1-xN (0.2<x?1) as a principal component, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and including AlyGa1-yN (0.2?y?0.55, y<x) as a principal component.
    Type: Application
    Filed: February 8, 2016
    Publication date: February 1, 2018
    Applicants: TAMURA CORPORATION, RIKEN
    Inventors: Yoshikatsu MORISHIMA, Kazuyuki IIZUKA, Akito KURAMATA, Hideki HIRAYAMA
  • Publication number: 20170213918
    Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.
    Type: Application
    Filed: July 24, 2015
    Publication date: July 27, 2017
    Applicants: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei SASAKI, Akito KURAMATA, Masataka HIGASHIWAKI
  • Publication number: 20170162655
    Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Inventors: Masaru TAKIZAWA, Akito KURAMATA
  • Patent number: 9595586
    Abstract: A semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: March 14, 2017
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Publication number: 20160322467
    Abstract: A semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Masaru TAKIZAWA, Akito KURAMATA
  • Patent number: 9412882
    Abstract: A Schottky barrier diode includes an n-type semiconductor layer including a Ga2O3-based compound semiconductor with n-type conductivity, and an electrode layer that is in Schottky-contact with the n-type semiconductor layer. A first semiconductor layer in Schottky-contact with the electrode layer and a second semiconductor layer having an electron carrier concentration higher than the first semiconductor layer are formed in the n-type semiconductor layer. The second semiconductor layer includes a ?-Ga2O3 substrate including a main plane rotated by an angle not less than 50° and not more than 90° with respect to a (100) plane thereof.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 9, 2016
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Publication number: 20160043238
    Abstract: A Schottky barrier diode includes an n-type semiconductor layer including a Ga2O3-based compound semiconductor with n-type conductivity, and an electrode layer that is in Schottky-contact with the n-type semiconductor layer. A first semiconductor layer in Schottky-contact with the electrode layer and a second semiconductor layer having an electron carrier concentration higher than the first semiconductor layer are formed in the n-type semiconductor layer. The second semiconductor layer includes a ?-Ga2O3 substrate including a main plane rotated by an angle not less than 50° and not more than 90° with respect to a (100) plane thereof.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: MASARU TAKIZAWA, Akito KURAMATA
  • Publication number: 20150364646
    Abstract: A crystal layered structure includes a Ga2O3 substrate and a nitride semiconductor layer and is capable of providing a light emitting element having high light output and a light emitting element includes this crystal layered structure. The crystal layered structure includes a Ga2O3 substrate a dielectric layer which is formed on the Ga2O3 substrate so as to partially cover the upper surface of the Ga2O3 substrate, and which has a refractive index difference of 0.15 or less relative to the Ga2O3 substrate and a nitride semiconductor layer which is formed on the Ga2O3 substrate with the dielectric layer interposed therebetween, and which is in contact with the dielectric layer and a portion not covered by the dielectric layer on the upper surface of the Ga2O3 substrate.
    Type: Application
    Filed: December 25, 2013
    Publication date: December 17, 2015
    Applicant: TAMURA CORPORATION
    Inventors: Yoshikatsu MORISHIMA, Shinkuro SATO, Ken GOTO, Kazuyuki IIZUKA, Akito KURAMATA
  • Patent number: 9171967
    Abstract: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n? -type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer, and an n+ semiconductor layer, which has a higher electron carrier concentration than the n semiconductor layer, are formed in the n-type semiconductor layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 27, 2015
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Patent number: 9153648
    Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga2O3 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AlN buffer layer formed on the Ga2O3 substrate, and a nitride semiconductor layer formed on the AlN buffer layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: October 6, 2015
    Assignees: TAMURA CORPORATION, KOHA CO, LTD.
    Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
  • Publication number: 20140332823
    Abstract: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n?-type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer, and an n+ semiconductor layer, which has a higher electron carrier concentration than the n semiconductor layer, are formed in the n-type semiconductor layer.
    Type: Application
    Filed: November 8, 2012
    Publication date: November 13, 2014
    Inventors: Masaru Takizawa, Akito Kuramata
  • Publication number: 20140048823
    Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga203 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer formed on the Ga203 substrate, and a nitride semiconductor layer formed on the AIN buffer layer.
    Type: Application
    Filed: April 3, 2012
    Publication date: February 20, 2014
    Applicants: KOHA CO., LTD., TAMURA CORPORATION
    Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
  • Patent number: 7507600
    Abstract: A semiconductor photodetecting device including a PIN photodiode formed on an SI-InP substrate; a buried optical waveguide portion formed on the SI-InP substrate and including the film thickness continuously increased toward the PIN photodiode and an InP clad layer covering the upper surface and the side surface of the InGaAsP core layer; and a ridge-shaped connection optical waveguide portion formed on the SI-InP substrate between the PIN photodiode and the buried optical waveguide portion and including the InGaAsP core layer and the InP clad layer selectively covering only the upper surface of the InGaAsP core layer.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Nami Yasuoka, Haruhiko Kuwatsuka, Akito Kuramata
  • Publication number: 20080131987
    Abstract: A method for fabricating a light-emitting device includes: forming a first semiconductor layer on a substrate; foaming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer, the second semiconductor layer having a conduction type opposite to that of the first semiconductor layer; and forming a recess so as to be penetrated through up to the first semiconductor layer from the second semiconductor layer by a first etching; and forming an inversely tapered shape to an inner wall of the recess by a second etching using an etching solution.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 5, 2008
    Applicant: EUDYNA DEVICES INC.
    Inventors: Kazuhiko Horino, Akito Kuramata, Hiroshi Yamamoto, Toshimitsu Kaneko
  • Patent number: 6990261
    Abstract: An optical circuit device including a substrate of a III–V group compound semiconductor, and a magnetic semiconductor layer having a chalcopyrite type crystal structure. The magnetic semiconductor having the chalcopyrite type crystal structure is a material which can provide Faraday effect, and the use of such material makes it possible to form the Faraday rotation element. Furthermore, the magnetic semiconductor having the chalcopyrite type crystal structure which can lattice-match with the substrates have little crystal defects, which can make a light loss of the Faraday rotation element small. The magnetic semiconductor of the chalcopyrite type crystal structure can provide large Verdet's constant, which makes it possible to reduce a length of the Faraday rotation element and resultantly makes it possible to micronize the optical circuit device.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: January 24, 2006
    Assignee: Fujitsu Limited
    Inventor: Akito Kuramata
  • Patent number: 6984840
    Abstract: An optical semiconductor device includes an SiC substrate having an n-type conductivity, and an AlGaN buffer layer having an n-type conductivity formed on the SiC substrate with a composition represented as AlxGa1-xN, wherein the AlGaN buffer layer has a carrier density in the range between 3×1018–1×1020 cm?3, and the compositional parameter x is larger than 0 but smaller than 0.4 (0<x<0.4).
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: January 10, 2006
    Assignee: Fujitsu Limited
    Inventors: Akito Kuramata, Shinichi Kubota, Kazuhiko Horino, Reiko Soejima