Patents by Inventor Akito Kuramata
Akito Kuramata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220149158Abstract: A Schottky barrier diode, including a first n-type semiconductor layer including a ?-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a ?-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The ?-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Inventors: Masaru TAKIZAWA, Akito KURAMATA
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Patent number: 11264241Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.Type: GrantFiled: July 9, 2018Date of Patent: March 1, 2022Assignees: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Commnications TechnologyInventors: Akito Kuramata, Shinya Watanabe, Kohei Sasaki, Kuniaki Yagi, Naoki Hatta, Masataka Higashiwaki, Keita Konishi
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Patent number: 11264466Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.Type: GrantFiled: February 26, 2020Date of Patent: March 1, 2022Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Publication number: 20200194560Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Masaru TAKIZAWA, Akito KURAMATA
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Publication number: 20200168460Abstract: A semiconductor substrate includes a single crystal Ga2O3-based substrate and a polycrystalline substrate that are bonded to each other. A thickness of the single crystal Ga2O3-based substrate is smaller than a thickness of the polycrystalline substrate, and a fracture toughness value of the polycrystalline substrate is higher than a fracture toughness value of the single crystal Ga2O3-based substrate.Type: ApplicationFiled: July 9, 2018Publication date: May 28, 2020Applicants: TAMURA CORPORATION, SICOXS Corporation, National Institute of Information and Communications TechnologyInventors: Akito KURAMATA, Shinya WATANABE, Kohei SASAKI, Kuniaki YAGI, Naoki HATTA, Masataka HIGASHIWAKI, Keita KONISHI
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Patent number: 10600874Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.Type: GrantFiled: February 17, 2017Date of Patent: March 24, 2020Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Patent number: 10230007Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.Type: GrantFiled: July 24, 2015Date of Patent: March 12, 2019Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGYInventors: Kohei Sasaki, Akito Kuramata, Masataka Higashiwaki
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Publication number: 20180033907Abstract: A nitride semiconductor template includes a Ga2O3 substrate, a buffer layer formed on the Ga2O3 substrate and including AlN as a principal component, a first nitride semiconductor layer formed on the buffer layer and including AlxGa1-xN (0.2<x?1) as a principal component, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and including AlyGa1-yN (0.2?y?0.55, y<x) as a principal component.Type: ApplicationFiled: February 8, 2016Publication date: February 1, 2018Applicants: TAMURA CORPORATION, RIKENInventors: Yoshikatsu MORISHIMA, Kazuyuki IIZUKA, Akito KURAMATA, Hideki HIRAYAMA
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Publication number: 20170213918Abstract: A semiconductor element includes a base substrate that includes a Ga2O3-based crystal having a thickness of not less than 0.05 ?m and not more than 50 ?m, and an epitaxial layer that includes a Ga2O3-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a Ga2O3-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer.Type: ApplicationFiled: July 24, 2015Publication date: July 27, 2017Applicants: TAMURA CORPORATION, National Institute of Information and Communications TechnologyInventors: Kohei SASAKI, Akito KURAMATA, Masataka HIGASHIWAKI
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Publication number: 20170162655Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Inventors: Masaru TAKIZAWA, Akito KURAMATA
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Patent number: 9595586Abstract: A semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.Type: GrantFiled: July 12, 2016Date of Patent: March 14, 2017Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Publication number: 20160322467Abstract: A semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.Type: ApplicationFiled: July 12, 2016Publication date: November 3, 2016Inventors: Masaru TAKIZAWA, Akito KURAMATA
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Patent number: 9412882Abstract: A Schottky barrier diode includes an n-type semiconductor layer including a Ga2O3-based compound semiconductor with n-type conductivity, and an electrode layer that is in Schottky-contact with the n-type semiconductor layer. A first semiconductor layer in Schottky-contact with the electrode layer and a second semiconductor layer having an electron carrier concentration higher than the first semiconductor layer are formed in the n-type semiconductor layer. The second semiconductor layer includes a ?-Ga2O3 substrate including a main plane rotated by an angle not less than 50° and not more than 90° with respect to a (100) plane thereof.Type: GrantFiled: October 20, 2015Date of Patent: August 9, 2016Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Publication number: 20160043238Abstract: A Schottky barrier diode includes an n-type semiconductor layer including a Ga2O3-based compound semiconductor with n-type conductivity, and an electrode layer that is in Schottky-contact with the n-type semiconductor layer. A first semiconductor layer in Schottky-contact with the electrode layer and a second semiconductor layer having an electron carrier concentration higher than the first semiconductor layer are formed in the n-type semiconductor layer. The second semiconductor layer includes a ?-Ga2O3 substrate including a main plane rotated by an angle not less than 50° and not more than 90° with respect to a (100) plane thereof.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: MASARU TAKIZAWA, Akito KURAMATA
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Publication number: 20150364646Abstract: A crystal layered structure includes a Ga2O3 substrate and a nitride semiconductor layer and is capable of providing a light emitting element having high light output and a light emitting element includes this crystal layered structure. The crystal layered structure includes a Ga2O3 substrate a dielectric layer which is formed on the Ga2O3 substrate so as to partially cover the upper surface of the Ga2O3 substrate, and which has a refractive index difference of 0.15 or less relative to the Ga2O3 substrate and a nitride semiconductor layer which is formed on the Ga2O3 substrate with the dielectric layer interposed therebetween, and which is in contact with the dielectric layer and a portion not covered by the dielectric layer on the upper surface of the Ga2O3 substrate.Type: ApplicationFiled: December 25, 2013Publication date: December 17, 2015Applicant: TAMURA CORPORATIONInventors: Yoshikatsu MORISHIMA, Shinkuro SATO, Ken GOTO, Kazuyuki IIZUKA, Akito KURAMATA
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Patent number: 9171967Abstract: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n? -type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer, and an n+ semiconductor layer, which has a higher electron carrier concentration than the n semiconductor layer, are formed in the n-type semiconductor layer.Type: GrantFiled: November 8, 2012Date of Patent: October 27, 2015Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Patent number: 9153648Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga2O3 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AlN buffer layer formed on the Ga2O3 substrate, and a nitride semiconductor layer formed on the AlN buffer layer.Type: GrantFiled: April 3, 2012Date of Patent: October 6, 2015Assignees: TAMURA CORPORATION, KOHA CO, LTD.Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
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Publication number: 20140332823Abstract: A Schottky barrier diode is provided with: an n-type semiconductor layer including Ga2O3-based compound semiconductors with n-type conductivity; and a Schottky electrode layer which is in Schottky-contact with the n-type semiconductor layer. An n?-type semiconductor layer, which has a relatively low electron carrier concentration and is brought into Schottky-contact with the Schottky electrode layer, and an n+ semiconductor layer, which has a higher electron carrier concentration than the n semiconductor layer, are formed in the n-type semiconductor layer.Type: ApplicationFiled: November 8, 2012Publication date: November 13, 2014Inventors: Masaru Takizawa, Akito Kuramata
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Publication number: 20140048823Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga203 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AIN buffer layer formed on the Ga203 substrate, and a nitride semiconductor layer formed on the AIN buffer layer.Type: ApplicationFiled: April 3, 2012Publication date: February 20, 2014Applicants: KOHA CO., LTD., TAMURA CORPORATIONInventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
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Patent number: 7507600Abstract: A semiconductor photodetecting device including a PIN photodiode formed on an SI-InP substrate; a buried optical waveguide portion formed on the SI-InP substrate and including the film thickness continuously increased toward the PIN photodiode and an InP clad layer covering the upper surface and the side surface of the InGaAsP core layer; and a ridge-shaped connection optical waveguide portion formed on the SI-InP substrate between the PIN photodiode and the buried optical waveguide portion and including the InGaAsP core layer and the InP clad layer selectively covering only the upper surface of the InGaAsP core layer.Type: GrantFiled: July 14, 2005Date of Patent: March 24, 2009Assignee: Fujitsu LimitedInventors: Nami Yasuoka, Haruhiko Kuwatsuka, Akito Kuramata