Abstract: A signal processing circuit has a plurality of first circuits each including a first-time-length-signal output circuit that outputs a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes and a second-time-length-signal output circuit that outputs the first time-length signal as a second time-length signal at timing based on a control signal. The signal processing circuit includes a second circuit that outputs the second time-length signal having the longest time length among a plurality of the second time-length signals output respectively from the plurality of first circuits.

Abstract: Distance measurement systems and devices that optimize avalanche photodiode bias voltage are disclosed. In one example, a distance measurement system a light emitting device that emits distance measurement light, and a photodetection device that receives reflected light of the distance measurement light. The photodetection device includes a pixel array with a plurality of pixels that respectively include avalanche photodiodes that detect the reflected light; a current measurement circuit that measures a total pixel current of the pixel array; and bias voltage control that controls avalanche photodiode bias voltage using a detection result of the current measurement circuit. The light emitting device also includes light emission control circuitry that controls a light quantity of the distance measurement light using the detection result of the current measurement circuit.

Abstract: A signal processing circuit in one aspect of the present disclosure includes a first circuit, a second circuit, an electric wire, and a third circuit. The first circuit has at least a first input terminal that receives a first signal and a first output terminal that outputs a second signal at least based on the first signal. The second circuit has at least a second input terminal that receives the second signal and a second output terminal that outputs a frequency-modulated second signal. The electric wire is electrically connected with the second output terminal. The third circuit has at least a third input terminal that receives the frequency-modulated second signal and a third output terminal that outputs a second signal demodulated to a frequency at the time of input to the first circuit. The electric wire is further electrically connected with other than the second output terminal and the third input terminal.

Abstract: A signal processing circuit (12) outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.

Abstract: A communication system according to the present disclosure includes a first communication unit that includes a first terminal, a transmission circuit configured to transmit a clock signal via the first terminal, a first resistor inserted into a path between the first terminal and a power supply, a first switch configured to couple the power supply and the first terminal to each other by being turned on, and a first controller configured to control an operation of the first switch, and a second communication unit that includes a second terminal coupled to the first terminal of the first communication unit via a first wiring line, a reception circuit configured to receive the clock signal via the second terminal, a power storage device, a second switch configured to couple the second terminal and the power storage device to each other by being turned on, and a second controller configured to control an operation of the second switch, the second communication unit being configured to operate by supply of a volta

Abstract: A signal processing circuit (13) has: a plurality of first circuits (41-1) each including a first-time-length-signal output circuit (51) configured to output a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes and a second-time-length-signal output circuit (52) configured to output the first time-length signal as a second time-length signal at timing based on a control signal; and a second circuit (42) configured to output the second time-length signal having the longest time length among a plurality of the second time-length signals output respectively from the plurality of first circuits (41-1).

Abstract: A communication system according to the present disclosure includes a first communication unit that includes a first terminal, a transmission circuit configured to transmit a clock signal via the first terminal, a first resistor inserted into a path between the first terminal and a power supply, a first switch configured to couple the power supply and the first terminal to each other by being turned on, and a first controller configured to control an operation of the first switch, and a second communication unit that includes a second terminal coupled to the first terminal of the first communication unit via a first wiring line, a reception circuit configured to receive the clock signal via the second terminal, a power storage device, a second switch configured to couple the second terminal and the power storage device to each other by being turned on, and a second controller configured to control an operation of the second switch, the second communication unit being configured to operate by supply of a volta

Abstract: The present technology relates to a control circuit, a communication device, and a communication system that enable cost reduction. A switch switches on or off connection between a pulled-up bus and a power storage unit. The pulled-up bus is a bus that is pulled up in a plurality of buses that are connected to a communication device and include at least one bus that is pulled up. The power storage unit stores electric power supplied from the pulled-up bus, and supplies the stored electric power as a power supply to the communication device. A control unit performs control to turn on or off the switch. The present technology can be applied to a communication system that performs I2C communication, for example.

Abstract: To control a drive voltage of a transistor to be constant in a circuit that captures signals. A duty ratio control unit changes a duty ratio of a predetermined input periodic signal and outputs the predetermined input periodic signal as an output periodic signal. A transistor is a transistor that outputs an input signal input to a source from a drain as an output signal. A charge control unit charges the condenser with a predetermined voltage in a case in which the output periodic signal is not at a specific level. A transistor drive unit applies the charged predetermined voltage between a gate and the source of the transistor in a case in which the output periodic signal is at the specific level.

Abstract: To control a drive voltage of a transistor to be constant in a circuit that captures signals. A duty ratio control unit changes a duty ratio of a predetermined input periodic signal and outputs the predetermined input periodic signal as an output periodic signal. A transistor is a transistor that outputs an input signal input to a source from a drain as an output signal. A charge control unit charges the condenser with a predetermined voltage in a case in which the output periodic signal is not at a specific level. A transistor drive unit applies the charged predetermined voltage between a gate and the source of the transistor in a case in which the output periodic signal is at the specific level.

Abstract: A signal generation circuit includes a phase difference detector configured to detect a phase difference between a certain oscillation signal of a plurality of oscillation signals and a predetermined reference signal; an oscillator to which a plurality of delay elements are connected annularly, the oscillator being configured to generate the plurality of oscillation signals depending on the detected phase difference; a low-speed signal generation circuit configured to generate a low-speed signal having a lower frequency than the oscillation signal; a detection circuit configured to detect a difference between a predetermined reference timing and a timing at which the low-speed signal has changed; a selection unit configured to select the oscillation signal so that the phase difference with respect to the reference signal is close to the detected difference; and an output unit configured to output the generated low-speed signal in synchronization with the selected oscillation signal.

Abstract: A clock generation circuit includes a delay clock generation unit configured to generate a predetermined number of delay clock signals having different delay time periods for a reference clock signal; a low-speed clock generation unit configured to generate a low-speed clock signal having a lower frequency than the reference signal in accordance with a control signal that controls a phase; a control signal processing unit configured to perform, on the control signal, a quantization process for quantizing a value of the control signal into the predetermined number of discrete values and a modulation process for distributing a quantization error in the quantization process in a band of frequencies higher than a predetermined frequency; a selection unit configured to select any one of the predetermined number of delay signals in accordance with the control signal; and an output unit configured to output the low-speed signal in synchronization with the selected signal.

Abstract: A clock generation circuit includes a delay clock generation unit configured to generate a predetermined number of delay clock signals having different delay time periods for a reference clock signal; a low-speed clock generation unit configured to generate a low-speed clock signal having a lower frequency than the reference signal in accordance with a control signal that controls a phase; a control signal processing unit configured to perform, on the control signal, a quantization process for quantizing a value of the control signal into the predetermined number of discrete values and a modulation process for distributing a quantization error in the quantization process in a band of frequencies higher than a predetermined frequency; a selection unit configured to select any one of the predetermined number of delay signals in accordance with the control signal; and an output unit configured to output the low-speed signal in synchronization with the selected signal.

Abstract: A signal generation circuit includes a phase difference detector configured to detect a phase difference between a certain oscillation signal of a plurality of oscillation signals and a predetermined reference signal; an oscillator to which a plurality of delay elements are connected annularly, the oscillator being configured to generate the plurality of oscillation signals depending on the detected phase difference; a low-speed signal generation circuit configured to generate a low-speed signal having a lower frequency than the oscillation signal; a detection circuit configured to detect a difference between a predetermined reference timing and a timing at which the low-speed signal has changed; a selection unit configured to select the oscillation signal so that the phase difference with respect to the reference signal is close to the detected difference; and an output unit configured to output the generated low-speed signal in synchronization with the selected oscillation signal.