Abstract: A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.

Abstract: A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.

Abstract: A latch circuit provided herein includes an input circuit including a PMOS transistor that is configured for input and enables a signal current to flow into the PMOS transistor; a first inverter comprising a first PMOS transistor, a first NMOS transistor, and a first node; a second inverter comprising a second PMOS transistor, a second NMOS transistor, and a second node. The signal current corresponds to a sense voltage from a sense amplifier. The first PMOS transistor and the first NMOS transistor are connected to each other through the first node, and the first node is connected to the input circuit. The second PMOS transistor and the second NMOS transistor are connected to each other through the second node. The first inverter and the second inverter are cascaded.

Abstract: In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel.

Abstract: A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line.

Abstract: A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line.

Abstract: In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel.

Abstract: A semiconductor device includes a rectangular chip having four sides, wires connected respectively to different external terminals, and a bonding pad disposed along one of the four sides of the rectangular chip and directly connected to the wires for connection to the different external terminals. Since the different external terminals are bonded directly to the bonding pad by the wires, a signal input from one of the external terminals via one of the wires can be sent to the other external terminal via the other wire.

Abstract: A semiconductor memory device (100) has been disclosed. A semiconductor memory device (100) may include a select circuit region (31), a reading circuit region (33), and a memory cell array region (30). Memory cell array region (30) may include proximal memory cells (11A) and distal memory cells (11B) with respect to a select circuit region (31) or a reading circuit region (33). Distal memory cells (11B) have a current drive characteristic that may be greater than a current drive characteristic of proximal memory cells (11A). In this way, compensation may be provided and a data propagation delay difference due to parasitic values may be decreased.

Abstract: A semiconductor memory device (100) has been disclosed. A semiconductor memory device (100) may include a select circuit region (31), a reading circuit region (33), and a memory cell array region (30). Memory cell array region (30) may include proximal memory cells (11A) and distal memory cells (11B) with respect to a select circuit region (31) or a reading circuit region (33). Distal memory cells (11B) have a current drive characteristic that may be greater than a current drive characteristic of proximal memory cells (11A). In this way, compensation may be provided and a data propagation delay difference due to parasitic values may be decreased.