Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A photocell for detecting light includes at least two tiers or structures, one disposed over the other, each tier having a metal-insulator-semiconductor (M-I-S) or a semiconductor-insulator-metal (S-I-M) structure. Each M-I-S structure includes a semiconductor diffusion layer capable of developing a depletion region, a thin insulator layer disposed on the diffusion layer, and a contact layer disposed on the thin insulator layer. Each S-I-M structure includes a contact layer, a thin insulator layer disposed on the contact layer, and a semiconductor diffusion layer disposed on the thin insulator layer, the semiconductor layer capable of developing a depletion region. When light is incident on each depletion region, a current indicative of the light detected in each depletion region flows through the respective contact layer. Also provided is a semiconductor-insulator-metal (S-I-M) structure that detects light. Two- and three-tiered photocells made of M-I-S and/or S-I-M structures are also provided.

Abstract: A photocell for detecting light includes at least two tiers or structures, one disposed over the other, each tier having a metal-insulator-semiconductor (M-I-S) or a semiconductor-insulator-metal (S-I-M) structure. Each M-I-S structure includes a semiconductor diffusion layer capable of developing a depletion region, a thin insulator layer disposed on the diffusion layer, and a contact layer disposed on the thin insulator layer. Each S-I-M structure includes a contact layer, a thin insulator layer disposed on the contact layer, and a semiconductor diffusion layer disposed on the thin insulator layer, the semiconductor layer capable of developing a depletion region. When light is incident on each depletion region, a current indicative of the light detected in each depletion region flows through the respective contact layer. Also provided is a semiconductor-insulator-metal (S-I-M) structure that detects light. Two- and three-tiered photocells made of M-I-S and/or S-I-M structures are also provided.

Abstract: A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.

Abstract: An FeRAM in which sensing occurs without a dummy cell, using an unselected bitline as a reference. The read cycle includes two opposed pulses on the drive line: the first pulse provides a data-dependent signal out of the selected cell, and the second pulse restores the bit line to a level such that the DC bias voltage on an unselected bitline provides an optimal reference.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: A metal oxide capacitor is manufactured by sequentially laminating a metal oxide film and a secon electrode on a first electrode. The metal oxide film is formed and then heat-treated in an atmosphere with an oxygen pressure higher than 1 atm.

Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

Abstract: A method for forming a ferroelectric material film, more particularly a lead zirconate titanate (PZT) film by the sol-gel method wherein a lowered oxidative sintering temperature may be adopted in preparing the ferroelectric material film with a perovskite crystalline structure, thereby reducing the risk of oxidation of metal electrodes and other circuits when the ferroelectric material film is employed as a dielectric in semiconductor devices, such as in a capacitor, for example. The method contemplates the preparation of a raw material solution containing an organometallic compound of a metallic element forming the ferroelectric material film, alkanolamine and/or stabilizer comprising a .beta.-diketone, with the concentration of the stabilizer being sufficient to provide a mole ratio to the total metal atoms of (stabilizer/total metal atoms)>3.

Abstract: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

Abstract: A method for forming a PZT strong dielectric film by the sol-gel technique, in which the thickness of the film is substantially no greater than 1000 .ANG.. In another aspect, the drying temperature of the raw material sol-gel solution for forming the PZT dielectric film is maintained within the range of 130.degree.-200.degree. C., and is particularly set lower than the boiling point of the stabilizer contained in the sol-gel raw material and higher than the boiling point of the solvent contained in the sol-gel raw material. As a result of performing the oxidative sintering treatment at a temperature at which perovskite crystals form, it becomes possible to readily form thin films exhibiting a (100) crystal orientation in particular. Additionally, completely crack-free thick films can be formed.

Abstract: A capacitor, electrode, or wiring structure having an alpha ray emitting source (in particular, a Pt electrode), and an alpha ray shielding layer 18, having at least one type selected from the group of simple metals of nickel, cobalt, copper, and tungsten, their compounds or alloys made of at least two types of these simple metals, and compounds and alloys made of these simple metals and silicon is provided. It is possible to shield off the alpha ray effectively, to suppress generation of soft errors, to enable the use of Pt and other new materials in making the electrodes and wiring, and to reduce the cost of the mold resin.