Abstract: A multiplexer includes three switching divisions each of which has one terminal connected to each of the signal terminals and the other terminal connected to a fourth switching division. A signal inputted through the selected signal terminal is outputted from the other signal terminal to the exterior by operating the fourth switching division.

Abstract: A memory system, wherein the respective byte memories 1 to 4 is configured so that data of word unit which are the targets of the parity calculation done by the parity calculation circuits 5 to 8 occupy respectively the same bit positions as those of the 4-word data of word unit, is provided with multiplexers 41 to 44 for connecting selectively to the data bus 29 the bit positions of the data of word unit selected by the word select control circuit 23 in such byte memories 1 to 4. The memory system is capable of improving the flexibility of the memory configuration by being eased of the limitation of the arrangement of bits which are the targets of parity calculation, and reducing the occupied areas of the write/read circuit on a chip as well as the electric power consumption.

Abstract: A bus width control circuit being arranged between a first bus and a second bus both of n-bits width, and comprising a buffer group being connected to the first bus and which split data of n-bits into partial data of m-bits and buffer them, a selector which connects each buffer to the second bus in parallel in the case where the effective data bus width of the second bus is n bits and which connects each buffer to a predetermined m bits of the second bus in the case where the effective data bus width of the second bus is m bits, and a control circuits thereof, and a control circuit which locates intact the n-bits data of the first bus in the second bus or by splitting it into partial data of m-bits in a predetermined portion of n-bits data and outputs them sequentially to the second bus, or which splits the n-bits data of the second bus into partial data of m-bits and buffers them in each buffer and then simultaneously outputs them to the first bus, or which sequentially buffers data whose m bits alone of the

Abstract: A delay circuit composed of a plurality of series circuits connected to each other in parallel, wherein each of series circuits is composed of a switching element made of FET like N-channel transistor and a capacitor. And a semiconductor system which allows proper connection of other semiconductor systems containing different AC charcteristics by delaying internal clock, input pulse signal or output pulse signal by applying the delay circuit embodied by the invention.