Patents by Inventor Akitoshi Takanashi

Akitoshi Takanashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220192029
    Abstract: There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 ?m thick having a surface having an arithmetic mean waviness Wa of 0.10 ?m or more and 0.25 ?m or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 16, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori SHIMIZU, Hiroto IIDA, Misato MIZOGUCHI, Akitoshi TAKANASHI, Makoto HOSOKAWA
  • Publication number: 20220183158
    Abstract: There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 ?m thick having a surface having an arithmetic mean waviness Wa of 0.10 ?m or more and 0.25 ?m or less and a valley portion void volume Vvv of 0.010 ?m3/?m2 or more and 0.028 ?m3/?m2 or less; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 9, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori SHIMIZU, Hiroto IIDA, Misato MIZOGUCHI, Akitoshi TAKANASHI, Makoto HOSOKAWA
  • Patent number: 7217464
    Abstract: The object is to provide a method of manufacturing electrodeposited copper foil with a carrier foil for high-temperature heat-resistance in which the peeling of the carrier foil is easy even by press working at temperatures of not less than 200°C.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: May 15, 2007
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Akitoshi Takanashi, Kenichiro Iwakiri, Akiko Sugimoto, Junshi Yoshioka, Shinichi Obata, Makoto Dobashi
  • Publication number: 20040170858
    Abstract: The object is to provide a method of manufacturing electrodeposited copper foil with a carrier foil for high-temperature heat-resistance in which the peeling of the carrier foil is easy even by press working at temperatures of not less than 200° C.
    Type: Application
    Filed: January 14, 2004
    Publication date: September 2, 2004
    Inventors: Akitoshi Takanashi, Kenichiro Iwakiri, Akiko Sugimoto, Junshi Yoshioka, Shinichi Obata, Makoto Dobashi