Patents by Inventor Akitsu Ayukawa

Akitsu Ayukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5420079
    Abstract: The disclosed invention is a process for fabricating a semiconductor device comprising the steps of:forming a gate electrode;covering the gate electrode and surface of the substrate with a layer of silicon dioxide;etching the silicon dioxide layer using an RIE method and an HF etching method to form a sidewall of silicon dioxide against each side of the gate electrode;injecting ions into the substrate at an acceleration energy within the range of about 10-20 KeV to minimize crystalline defects in the substrate caused by ion injection;heating the entire substrate in two successive stages: (a) initially at a first temperature within the range of 700.degree.-850.degree. C. for approximately one hour to recover the crystallinity of the substrate damaged in the injecting step and to inhibit diffusion of impurities; and (b) then at a second temperature within the range of 900.degree.-1100.degree. C. for 5-15 seconds to form a shallow depth diffusion region in the substrate.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: May 30, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeo Onishi, Akitsu Ayukawa, Kenichi Tanaka
  • Patent number: 5411904
    Abstract: A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: May 2, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimitsu Yamauchi, Kenichi Tanaka, Keizo Sakiyama, Akitsu Ayukawa
  • Patent number: 5348900
    Abstract: A process for manufacturing a semiconductor device, including the steps of: forming a oxide film over the entire surface of a semiconductor substrate formed with a gate electrode having side walls on opposite sides thereof with intervention of a gate oxide film, followed by implanting an impurity into a predetermined region; subjecting the substrate to a first heat treatment; removing the oxide film existing in the predetermined region; and subjecting the substrate to a second heat treatment in an ammonia or oxygen gas atmosphere.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: September 20, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitsu Ayukawa, Shigeo Onishi
  • Patent number: 5322810
    Abstract: A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portion as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the sur
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: June 21, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitsu Ayukawa, Hiroshi Ishihara, Shigeo Onishi
  • Patent number: 5298446
    Abstract: A process for producing a semiconductor device comprising the steps of:(a) on a semiconductor Si substrate having a gate electrode formed thereon through the intermediary of an SiO.sub.2 film,i) forming as side wall of SiO.sub.2 on the side of said gate electrode followed by formation of an SiN film over the entire surface of the Si substrate, orii) forming on the entire surface of said substrate, an SiO.sub.2 film and and SiN film in sequence, followed by formation of a side wall of SiO.sub.2 on the side of said gate electrode;(b) injecting ions into said substrate; and(c) subjecting said substrate to a heat treatment with or without removal of the side wall of SiO.sub.2, thereby forming a diffusion region in the substrate.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: March 29, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeo Onishi, Akitsu Ayukawa, Kenichi Tanaka
  • Patent number: 5217912
    Abstract: A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portions as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the su
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: June 8, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitsu Ayukawa, Hiroshi Ishihara, Shigeo Onishi
  • Patent number: 5183770
    Abstract: A method for fabricating a semiconductor device in which diffusion regions are formed in a silicon substrate with use of a gate electrode parts having side walls as a mask, including the steps of: (a) forming a gate electrode on a silicon substrate with a gate oxide interposed therebetween; (b) depositing an insulation film to entirely cover the substrate and the gate electrode, followed by depositing a polysilicon or amorphous silicon layer on the insulation film; (c) forming side walls of SiO.sub.2 on lateral sides of the gate electrode covered with the insulation film and the polysilicon or amorphous silicon layer, followed by ion implantation; and (d) subjecting the resulting substrate to a heat treatment at a medium temperature after removal of the side walls, followed by stacking an interlayer insulator after removal of the polysilicon or amorphous silicon layer, and subjecting the resultant to a heat treatment at a high temperature.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: February 2, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akitsu Ayukawa, Shigeo Onishi