Patents by Inventor Akitsugu Hatazaki
Akitsugu Hatazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887826Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a stage, a backing plate and an earth shield. The stage is configured to hold a substrate that a film is to be deposited on. The backing plate faces the stage and is configured such that a target containing a film deposition material is to be joined. The earth shield has an opening configured to enclose the target, and a plurality of through holes provided over a whole circumference of a circumferential part of the opening.Type: GrantFiled: June 16, 2021Date of Patent: January 30, 2024Assignee: Kioxia CorporationInventors: Takashi Izumi, Akitsugu Hatazaki
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Publication number: 20220384466Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.Type: ApplicationFiled: December 6, 2021Publication date: December 1, 2022Applicant: Kioxia CorporationInventors: Takashi IZUMI, Akitsugu HATAZAKI, Shingo NAKAJIMA
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Patent number: 11462561Abstract: According to one embodiment, a semiconductor device includes: a wiring layer including a first metallic film provided on an oxide film, a second metallic film provided on the first metallic film, and a polysilicon film provided on the second metallic film; and an element layer provided on the wiring layer and including semiconductor elements electrically connected to the first metallic film. Standard Gibbs energy of formation of a first metal included in the first metallic film is lower than that of a second metal included in the second metallic film.Type: GrantFiled: August 28, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Takashi Izumi, Akitsugu Hatazaki, Masaaki Hatano, Tatsumi Usami
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Publication number: 20220301837Abstract: A film deposition apparatus according to an embodiment includes a target including a film deposition material, a backing plate to which the target is to be joined, and a magnet disposed above the backing plate. The backing plate includes a first portion facing the magnet and a second portion in which the intensity of a magnetic field generated by the magnet is lower than in the first portion, the thermal conductivity of a first material included in the first portion is higher than that of a second material included in the second portion, and the Young's modulus of the second material is higher than that of the first material.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventor: Akitsugu HATAZAKI
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Publication number: 20220302023Abstract: A semiconductor device according to the present embodiment comprises a first electrode film. An interlayer dielectric film is provided on the first electrode film. A contact plug is provided in a contact hole that penetrates through the interlayer dielectric film and reaches the first electrode film. The contact plug includes a first metal film and a first conductive film configured to cover an inner wall of an upper portion of the contact hole. The contact plug includes a second metal film configured to cover the first conductive film on the inner wall of the upper portion of the contact hole and cover an inner wall of a lower portion of the contact hole. The contact plug includes a second conductive film configured to be filled inside the second metal film in the contact hole.Type: ApplicationFiled: August 31, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventor: Akitsugu HATAZAKI
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Publication number: 20220076934Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a stage, a backing plate and an earth shield. The stage is configured to hold a substrate that a film is to be deposited on. The backing plate faces the stage and is configured such that a target containing a film deposition material is to be joined. The earth shield has an opening configured to enclose the target, and a plurality of through holes provided over a whole circumference of a circumferential part of the opening.Type: ApplicationFiled: June 16, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Takashi IZUMI, Akitsugu HATAZAKI
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Publication number: 20210407938Abstract: A semiconductor device comprises a first chip including a first semiconductor substrate, a first semiconductor element on the first semiconductor substrate, a first wiring layer to be connected to the first semiconductor element, and a first pad to be connected to the first wiring layer, and a second chip including a second semiconductor substrate, a second semiconductor element on the second semiconductor substrate, a second wiring layer to be connected to the second semiconductor element, and a second pad to be connected to the second wiring layer and joined to the first pad. At least one of the first pad and the second pad includes a first metal layer to be joined to the other pad, a second metal layer having a coefficient of thermal expansion higher than that of the first metal layer, and a barrier metal layer between the first metal layer and the second metal layer.Type: ApplicationFiled: September 9, 2021Publication date: December 30, 2021Applicant: Kioxia CorporationInventors: Akitsugu HATAZAKI, Atsushi KATO
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Publication number: 20210074722Abstract: According to one embodiment, a semiconductor device includes: a wiring layer including a first metallic film provided on an oxide film, a second metallic film provided on the first metallic film, and a polysilicon film provided on the second metallic film; and an element layer provided on the wiring layer and including semiconductor elements electrically connected to the first metallic film. Standard Gibbs energy of formation of a first metal included in the first metallic film is lower than that of a second metal included in the second metallic film.Type: ApplicationFiled: August 28, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Takashi Izumi, Akitsugu Hatazaki, Masaaki Hatano, Tatsumi Usami
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Patent number: 10825770Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.Type: GrantFiled: March 11, 2019Date of Patent: November 3, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu Hatazaki, Hiroko Tahara, Naomi Fukumaki, Masayuki Kitamura, Takashi Ohashi
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Patent number: 10748761Abstract: A semiconductor manufacturing apparatus includes at least one UV lamp provided at a position facing a surface of a semiconductor substrate arranged to irradiate the surface of the semiconductor substrate with UV light, and a shutter disposed between the surface of the semiconductor substrate and the at least one UV lamp and configured to block UV light emitted by the UV lamp. The shutter includes a first movable part movable in a first direction being an in-plane direction parallel to the semiconductor substrate, and a second movable part movable in a second direction being an in-plane direction perpendicular to the first direction, the second movable part being movable independently of the first movable part.Type: GrantFiled: March 1, 2019Date of Patent: August 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu Hatazaki, Kotaro Nomura
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Publication number: 20200091081Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.Type: ApplicationFiled: March 11, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu HATAZAKI, Hiroko Tahara, Naomi Fukumaki, Masayuki Kitamura, Takashi Ohashi
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Publication number: 20200075326Abstract: A semiconductor manufacturing apparatus includes at least one UV lamp provided at a position facing a surface of a semiconductor substrate arranged to irradiate the surface of the semiconductor substrate with UV light, and a shutter disposed between the surface of the semiconductor substrate and the at least one UV lamp and configured to block UV light emitted by the UV lamp. The shutter includes a first movable part movable in a first direction being an in-plane direction parallel to the semiconductor substrate, and a second movable part movable in a second direction being an in-plane direction perpendicular to the first direction, the second movable part being movable independently of the first movable part.Type: ApplicationFiled: March 1, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Akitsugu HATAZAKI, Kotaro NOMURA
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Patent number: 8878364Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process.Type: GrantFiled: February 15, 2013Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Morita, Akitsugu Hatazaki, Kazumasa Ito, Hiroshi Toyoda
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Publication number: 20140054782Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a high melting metal film on a side wall and a bottom surface of the opening; forming a seed film of copper (Cu) on the high melting metal film; performing nitriding process after the seed film is formed; and performing electroplating process, in which a Cu film is buried in the opening while energizing the seed film after performing nitriding process.Type: ApplicationFiled: February 15, 2013Publication date: February 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Toshiyuki Morita, Akitsugu Hatazaki, Kazumasa Ito, Hiroshi Toyoda
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Publication number: 20080083990Abstract: A semiconductor device including a copper layer, an aluminum containing layer, and a barrier metal layer having a laminated structure of a titanium layer and a titanium oxide layer formed between the copper layer and the aluminum containing layer.Type: ApplicationFiled: August 23, 2007Publication date: April 10, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akitsugu Hatazaki, Jota Fukuhara, Tomio Katata, Junichi Wada
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Patent number: 7095124Abstract: A semiconductor device comprises a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate and a sealing resin layer which coats the semiconductor chip. The sealing resin layer meets, in coefficient of linear expansion (?) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1) E<0.891/{(???s)2×h}??(1) where E represents the Young's modulus (GPa) of the sealing resin at room temperature; ? represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature; ?s represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; and h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.Type: GrantFiled: October 28, 2004Date of Patent: August 22, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Akitsugu Hatazaki
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Patent number: 7067922Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; at least one layer of a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less, an entire layer of the first insulating film being separated at least near four corners of the semiconductor substrate by a lacking portion that extends along the four corners; and a second insulating film covering a side face of the entire layer of the first insulating film in the lacking portion on a center side of the semiconductor substrate and having a relative dielectric constant of over 3.8.Type: GrantFiled: March 26, 2004Date of Patent: June 27, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Hasunuma, Akitsugu Hatazaki
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Publication number: 20050121808Abstract: A semiconductor device comprises a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate and a sealing resin layer which coats the semiconductor chip. The sealing resin layer meets, in coefficient of linear expansion (?) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1) E<0.891/{(???s)2×h}??(1) where E represents the Young's modulus (GPa) of the sealing resin at room temperature; ? represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature; ?s represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; and h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.Type: ApplicationFiled: October 28, 2004Publication date: June 9, 2005Inventors: Masahiko Hasunuma, Akitsugu Hatazaki
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Publication number: 20040245642Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; at least one layer of a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less, an entire layer of the first insulating film being separated at least near four corners of the semiconductor substrate by a lacking portion that extends along the four corners; and a second insulating film covering a side face of the entire layer of the first insulating film in the lacking portion on a center side of the semiconductor substrate and having a relative dielectric constant of over 3.8.Type: ApplicationFiled: March 26, 2004Publication date: December 9, 2004Inventors: Masahiko Hasunuma, Akitsugu Hatazaki