Abstract: An operation model generator includes one or more memories, and one or more processors configured to perform acquisition of signal information indicating signal values of an input signal and an output signal in a first register transfer level operation model of a logic circuit, and generate a hardware description language operation model of the logic circuit in accordance with the acquired signal information.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to generate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A memory construction apparatus for automatically forming a logical memory space, thereby making it possible to design an integrated circuit efficiently. A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical conditions defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to generate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.

Abstract: A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.