Abstract: Electrode pads disposed on a first surface of a semiconductor element include a first pad located close to a corner and a second pad located apart from the corner compared with the first pad. A first wire connected to the first pad has a smaller Young's modulus than a second wire connected to the second pad. A thickness of an intermetallic compound layer formed by the first wire and the first pad is larger than a thickness of an intermetallic compound layer formed by the second wire and the second pad.

Abstract: Electrode pads disposed on a first surface of a semiconductor element include a first pad located close to a corner and a second pad located apart from the corner compared with the first pad. A first wire connected to the first pad has a smaller Young's modulus than a second wire connected to the second pad. A thickness of an intermetallic compound layer formed by the first wire and the first pad is larger than a thickness of an intermetallic compound layer formed by the second wire and the second pad.

Abstract: In an electronic device, a silicone adhesive bonding first and second members is made from a composition comprising: (A) 100 parts by mass of an organopolysiloxane containing in one molecule at least two alkenyl groups and being free of silicon-bonded hydroxyl and alkoxy groups wherein the content of cyclic siloxanes having 4 to 20 siloxane units is at most 0.1 mass %; (B) an organopolysiloxane containing in one molecule at least two silicon-bonded hydrogen atoms and being free of an alkenyl group, and silicon-bonded hydroxyl and alkoxy groups; (C) at least 0.05 parts by mass of an adhesion promoter; (D) 100 to 2000 parts by mass of a thermally conductive filler; and (E) a hydrosilylation-reaction catalyst. (B) is contained such that the silicon-bonded hydrogen atoms is in the range of 0.5 to 10 mol per 1 mol of the alkenyl groups of (A), and the sum of (B) and (C) is 0.5 to 10 mass % of the sum of (A), (B) and (C).

Abstract: Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.

Abstract: An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

Abstract: A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a semiconductor element having a pn-junction is included in the semiconductor substrate. The semiconductor integrated circuit device having the SOI structure is formed with a semiconductor layer, or SOI layer, on a p-type semiconductor substrate through a buried insulating film and further with semiconductor circuit elements serving as functional elements at the SOI layer thus formed. As a protection transistor to protect the semiconductor circuit elements, a MOSFET may be formed in which n-type diffusion layers are formed in the semiconductor substrate. The n-type diffusion layers of the MOSFET are to be surrounded by p-type diffusion layers more highly doped than the semiconductor substrate.

Abstract: A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed.

Abstract: In a semiconductor integrated circuit device having an input protection circuit element such as a diode formed in the semiconductor substrate, the leak current is suppressed. An nMOS transistor and a pMOS transistor that constitute a CMOS inverter circuit are formed using a SOI structure. An n-type diffusion layer and p-type diffusion layer are formed within the semiconductor substrate to thereby construct a protective diode that forms an input protection circuit for the CMOS inverter circuit. By surrounding the outer periphery of the n-type diffusion layer with the p-type diffusion layer, the depletion layer that is formed at an interface between the semiconductor substrate and a buried insulation film therein is cut off by the p-type diffusion layer, thereby suppressing the leak current between the n-type diffusion layer and the p-type diffusion layer.

Abstract: A semiconductor device comprising: a semiconductor substrate; a diffused region extending from the surface and to the inside of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate and having a contact hole located through which the diffused region is exposed; a first conductor layer formed on a portion of the first insulating layer and connected so the diffused region through the first contact hole; and an insulator section made of an oxide of the substance of the first conductor layer and formed on another portion of the first insulating layer to surround the first conductor layer.

Abstract: A semiconductor device of SOI structure formed by the mesa isolation method, which can sufficiently reduce the wiring capacitance even if the width of the isolation trench is large. An SOI layer which constitutes an element region is formed by forming a buried oxide film in a silicon substrate, forming an isolation trench in the buried oxide film and burying an isolating material in the isolation trench. By the formation of the SOI layer with the isolating material, a dummy SOI layer is formed in a field part other than the element region. Then, by the formation of a MOSFET gate wiring on the dummy SOI layer, the wiring capacitance is reduced. Furthermore, the dummy SOI layer is completely depleted when the MOSFET threshold value is applied to the gate wiring.

Abstract: A protective circuit that can maintain effectiveness when excess voltages of both polarities are applied is placed between the input terminal of an internal CMOS inverter and an input pad. The protective circuit includes a protective resistor, a P-channel MOSFET and an N-channel MOSFET. The N-channel MOSFET is placed between a connecting line and a ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET is placed between the connecting line and the ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET releases excess negative voltage from the outside using ON-state current and the N-channel MOSFET releases excess positive voltage from the outside using ON-state current.

Abstract: A semiconductor device of an SOIMOSFET comprising a semiconductor substrate, an insulating layer and a thin film single-crystalline semiconductor layer, the insulating layer containing a floating electrically conductive layer buried therein at a portion corresponding to the channel, the floating electrically conductive layer being electrically insulated from the other portions, the semiconductor device further comprising an electrode adjacent to the floating electrically conductive layer for applying a voltage by which an electric charge is injected into and stored in the floating electroconductive layer.

Abstract: The present invention is intended to provide a method of fabricating an EEPROM having excellent endurance characteristics. A work obtained by processing a substrate (1) by a wafer processing process including a passivating process and having a tunnel oxide film, an aluminum wiring film and a passivation film is subjected to a low-temperature heat treatment employing a processing temperature of about 250.degree. C. and a processing time on the order of 50 hr in a thermostatic oven (20) in the presence of nitrogen gas. The low-temperature heat treatment reduces trap sites produced in the tunnel oxide film by a plasma CVD process carried out to form the passivation film to repair the tunnel oxide film damaged by the plasma CVD process and to improve the endurance characteristics. The aluminum wiring film is not deteriorated by the low-temperature heat treatment because the low-temperature heat treatment employs a relatively low processing temperature.