Patents by Inventor Akiyoshi Kudo
Akiyoshi Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120099614Abstract: A semiconductor laser device of the present invention includes: a substrate; a cladding layer of a first conductivity type formed above one of surfaces of the substrate; an active layer formed above the cladding layer of the first conductivity type; a cladding layer of a second conductivity type formed above the active layer, and having a ridge and a planar portion; a dielectric film formed on a lower portion of a side surface of the ridge and on the planar portion; a first electrode formed on an other one of the surfaces of the substrate; a second electrode formed above the ridge; a third electrode formed over the second electrode and the dielectric film to cover the ridge and the planar portion; and a cavity provided between the third electrode and at least a part of the side surface of the ridge.Type: ApplicationFiled: October 18, 2011Publication date: April 26, 2012Applicant: PANASONIC CORPORATIONInventors: Tomohiro YAMAZAKI, Akiyoshi KUDO, Kouji MAKITA
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Publication number: 20110142089Abstract: A first semiconductor layer, an active layer, a second semiconductor layer, and a contact layer are sequentially stacked on a substrate. A ridge portion extending between both facets of a resonator is provided in the second semiconductor layer and the contact layer. A current confining layer is formed to be in contact with the ridge portion. The current confining layer has an opening on an upper surface of the ridge portion. A first electrode in contact with the contact layer is formed in the opening. A second electrode is provided on the first electrode. A non-current injection portion in contact with the contact layer is provided on the upper surface of the ridge portion near the resonator facet. The current confining layer and the non-current injection portion are formed of the same dielectric film. The second electrode is spaced apart from an upper surface region of the non-current injection portion.Type: ApplicationFiled: November 1, 2010Publication date: June 16, 2011Inventor: Akiyoshi KUDO
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Publication number: 20100046566Abstract: A semiconductor light emitting device includes at least a first cladding layer of a first conductive type, an active layer, a second cladding layer of a second conductivity type, and a contact layer of the second conductivity type stacked in this order on a substrate, and further includes a ridge portion including the second cladding layer and the contact layer. On the second cladding layer, are formed a dielectric film which covers the ridge portion and has an opening selectively exposing a top of the ridge portion, and an electrode in contact with a top surface and a side surface of the contact layer exposed from the dielectric film. The dielectric film includes a no-current injection region which covers an end of the ridge portion to block current injection to the active layer, and the no-current injection region of the dielectric film is in contact with the contact layer.Type: ApplicationFiled: May 29, 2009Publication date: February 25, 2010Inventor: Akiyoshi KUDO
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Publication number: 20060281237Abstract: A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs layer formed on a GaAs substrate is to be formed; forming a p-type gate region by solid-phase diffusion which is performed by processes of rapid heating and fast cooling; removing the ZnO with wet etching using tartaric acid and the like so as to expose the p-type gate region; and forming the gate electrode on the exposed p-type gate region.Type: ApplicationFiled: May 12, 2006Publication date: December 14, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Akiyoshi Kudo, Yoshiharu Anda, Akiyoshi Tamura
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Patent number: 6998225Abstract: A method of producing a compound semiconductor device using a lift-off process. The lift-off process includes forming a resist mask having an electrode opening on an active layer of a compound semiconductor that is on a substrate of a compound semiconductor; forming a metal layer on the resist mask and the active layer in the electrode opening; and dissolving the resist mask and removing the metal layer on the resist mask, leaving the metal layer on the active layer in the electrode opening as an electrode. The resist mask is removed sufficiently by using a resist remover consisting essentially of at least one compound selected from an amine-including compound and nitrogen-including cyclic compounds so that the residual resist mask need not be removed by ashing.Type: GrantFiled: April 9, 2003Date of Patent: February 14, 2006Assignees: Mitsubishi Denki Kabushiki Kaisha, EKC Technology Kabushiki KaishaInventors: Akiyoshi Kudo, Hiroshi Kobayashi, Takanori Matsumoto
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Patent number: 6653667Abstract: A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.Type: GrantFiled: July 2, 2002Date of Patent: November 25, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akiyoshi Kudo
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Publication number: 20030194656Abstract: The present invention provides a method of producing a compound semiconductor device having a lift-off process. The lift-off process includes a step of forming a resist mask having an electrode opening on an active layer of a compound semiconductor formed on a substrate of a compound semiconductor; a step of forming a metal layer on the resist mask and the active layer in the electrode opening; and a releasing step of dissolving the resist mask and removing the metal layer formed on the resist mask to leave the metal layer on the active layer in the electrode opening as an electrode. In the releasing step, the resist mask is removed sufficiently by using a resist remover essentially consisting one or more compounds selected from a group consisting of an amine-including compound and nitrogen-including cyclic compounds so that the residual resist mask need not be removed by ashing.Type: ApplicationFiled: April 9, 2003Publication date: October 16, 2003Applicants: Mitsubishi Denki Kabushiki Kaisha, EKC Technology Kabushiki KaishaInventors: Akiyoshi Kudo, Hiroshi Kobayashi, Takanori Matsumoto
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Publication number: 20030006426Abstract: A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.Type: ApplicationFiled: July 2, 2002Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Akiyoshi Kudo
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Patent number: 5801069Abstract: A method of fabricating a thin film piezoelectric device includes preparing a semiconductor substrate having a surface; forming an etch stopping layer having an etching rate on the surface of the semiconductor substrate; forming a first semiconductor layer having an etching rate higher than the etching rate of the etch stopping layer on the etch stopping layer; forming a first electrode on a region of the first semiconductor layer; forming a piezoelectric film on the first electrode; forming a second electrode on the piezoelectric film; and etching a portion of the first semiconductor layer where the first electrode, the piezoelectric film, and the second electrode overlap, from the surface of the first semiconductor layer, selectively with respect to the etch stopping layer, thereby forming a cavity in the first semiconductor layer.Type: GrantFiled: January 31, 1996Date of Patent: September 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenichi Harada, Takeshi Kuragaki, Osamu Ishihara, Kazuhiko Sato, Akiyoshi Kudo
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Patent number: 5530272Abstract: A compound semiconductor device includes a carrier supply layer supplying free charge carriers and having high dopant impurity concentration regions with a prescribed width, disposed in stripe shapes along a main current flow direction, parallel to each other, and spaced at an interval, and a carrier channel layer to which free charge carriers are supplied from the carrier supply layer including an electron channel having a high free carrier density at portions corresponding to respective high dopant impurity concentration regions of the carrier supply layer in the vicinity of a heterojunction interface. The heterojunction interface formed by the carrier channel layer and the carrier supply layer has a periodic undulating shape with convex portions and valley portions in stripe shapes extending parallel to the main current flow direction.Type: GrantFiled: October 26, 1994Date of Patent: June 25, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akiyoshi Kudo, Kazuo Hayashi