Patents by Inventor Akiyoshi Mutoh

Akiyoshi Mutoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8115851
    Abstract: A solid-state image capturing apparatus according to the present invention includes: a plurality of photoelectric conversion sections; a charge accumulation section; and a charge readout section, the apparatus further includes: a semiconductor substrate including a plurality of diffusion layers formed thereabove, the diffusion layers constituting the photoelectric conversion sections, the charge accumulation section and the charge readout section; a readout gate electrode formed above the semiconductor substrate and constituting the charge readout section; an insulation sidewall formed on a side surface of the readout gate electrode; and a surface diffusion layer constituting the photoelectric conversion sections, which is positioned in a self-aligning manner with respect to the readout gate electrode by the insulation sidewall.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: February 14, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akiyoshi Mutoh
  • Publication number: 20100149397
    Abstract: A solid-state image capturing apparatus according to the present invention includes: a plurality of photoelectric conversion sections; a charge accumulation section; and a charge readout section, the apparatus further includes: a semiconductor substrate including a plurality of diffusion layers formed thereabove, the diffusion layers constituting the photoelectric conversion sections, the charge accumulation section and the charge readout section; a readout gate electrode formed above the semiconductor substrate and constituting the charge readout section; an insulation sidewall formed on a side surface of the readout gate electrode; and a surface diffusion layer constituting the photoelectric conversion sections, which is positioned in a self-aligning manner with respect to the readout gate electrode by the insulation sidewall.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 17, 2010
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Akiyoshi Mutoh
  • Patent number: 7560781
    Abstract: A semiconductor device includes a first insulating layer and a second insulating layer in a trench. The first insulating layer insulates two MOSFETs from each other, and the second insulating layer has a true stress opposite to a true stress of the first insulating layer. The second insulating layer includes two regions of different true stresses. This enables a drain current flow in each MOSFET to be independently controlled in a semiconductor device that employs a STI method for element isolation.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: July 14, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihisa Gotoh, Kenichi Azuma, Kouichi Takeuchi, Akiyoshi Mutoh
  • Publication number: 20090050997
    Abstract: A solid-state image capturing device having a plurality of light receiving sections for performing photoelectrical conversion on and capturing image light from a subject is provided. In the light receiving sections, a low concentration opposite conductivity layer is provided either on a single conductivity substrate or a single conductivity layer, a high concentration opposite conductivity layer having a higher impurity concentration than the low concentration opposite conductivity layer is provided on the low concentration opposite conductivity layer, and a photodiode is constituted by a PN junction of the single conductivity substrate or the single conductivity layer and the low concentration opposite conductivity layer.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 26, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Akiyoshi Mutoh
  • Publication number: 20070178638
    Abstract: A semiconductor device includes a first insulating layer and a second insulating layer in a trench. The first insulating layer insulates two MOSFETs from each other, and the second insulating layer has a true stress opposite to a true stress of the first insulating layer. The second insulating layer includes two regions of different true stresses. This enables a drain current flow in each MOSFET to be independently controlled in a semiconductor device that employs a STI method for element isolation.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 2, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshihisa Gotoh, Kenichi Azuma, Kouichi Takeuchi, Akiyoshi Mutoh