Abstract: A vehicle security device for improving the security level of a vehicle. The vehicle security device is connected to an engine and communicates with a portable device. A smart ECU performs a first coded communication to establish mutual authentication with the portable device. An ID code box is connected to the smart ECU, has a first code and a second code, and does not communicate with the portable device. The ID code box performs a second coded communication using the first code to establish a second mutual authentication with the smart ECU. An engine ECU performs a third coded communication using the second code to establish a third mutual authentication with the ID code box. The engine ECU enables the engine to be started when every one of the first, second, and third mutual authentications are established.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A vehicle security device for improving the security level of a vehicle. The vehicle security device is connected to an engine and communicates with a portable device. A smart ECU performs a first coded communication to establish mutual authentication with the portable device. An ID code box is connected to the smart ECU, has a first code and a second code, and does not communicate with the portable device. The ID code box performs a second coded communication using the first code to establish a second mutual authentication with the smart ECU. An engine ECU performs a third coded communication using the second code to establish a third mutual authentication with the ID code box. The engine ECU enables the engine to be started when every one of the first, second, and third mutual authentications are established.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal.

Abstract: A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor.