Patents by Inventor Akiyoshi Saitou
Akiyoshi Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8966433Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignee: Fujitsu LimitedInventor: Akiyoshi Saitou
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Patent number: 8744810Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.Type: GrantFiled: February 9, 2011Date of Patent: June 3, 2014Assignee: Fujitsu LimitedInventors: Nobutaka Itoh, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
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Publication number: 20130328156Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.Type: ApplicationFiled: March 15, 2013Publication date: December 12, 2013Applicant: FUJITSU LIMITEDInventor: Akiyoshi SAITOU
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Patent number: 8522191Abstract: The design aiding device includes a processor that creates assembled model data, representing an assembled model that assumes arrangement of the part on the board, on the basis of the board data and the part data stored in the first storing section and the second storing section, respectively. The processor includes a recognizing section that recognizes a mounting face of a part model defined by the part data, the mounting face being mounted on a board model defined by the board data; and an arrangement processing section that creates the assembled model data by arranging the part model on the board model on the basis of the mounting face recognized by the recognizing section.Type: GrantFiled: August 17, 2011Date of Patent: August 27, 2013Assignee: Fujitsu LimitedInventors: Youji Uchikura, Akiyoshi Saitou, Yukihiko Onishi, Manabu Nakagawa
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Patent number: 8304662Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.Type: GrantFiled: June 1, 2007Date of Patent: November 6, 2012Assignee: Fujitsu LimitedInventors: Akiyoshi Saitou, Takeshi Midorikawa, Toru Kuraishi, Chikayuki Kumagai, Masashi Fujimoto, Kenichiro Abe
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Patent number: 8222540Abstract: A printed wiring board having an insulating core; a plurality of vias having axes parallel to and at equal distance from a reference axis and passing through the core; a first conductive film formed on a front surface of the core from the reference axis to each of the individual vias; a first insulating film stacked on the front surface of the core and covering the first conductive film; a first connecting via having an axis identical to the reference axis and passing through the first stacked film; a second conductive film formed on a back surface of the core from the reference axis to each of the individual vias; a second insulating film stacked on the back surface of the core and covering the second conductive film; and a second connecting via having an axis identical to the reference axis and passing through the second stacked film.Type: GrantFiled: May 7, 2010Date of Patent: July 17, 2012Assignee: Fujitsu LimitedInventor: Akiyoshi Saitou
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Publication number: 20120059499Abstract: The design aiding device includes a processor that creates assembled model data, representing an assembled model that assumes arrangement of the part on the board, on the basis of the board data and the part data stored in the first storing section and the second storing section, respectively. The processor includes a recognizing section that recognizes a mounting face of a part model defined by the part data, the mounting face being mounted on a board model defined by the board data; and an arrangement processing section that creates the assembled model data by arranging the part model on the board model on the basis of the mounting face recognized by the recognizing section.Type: ApplicationFiled: August 17, 2011Publication date: March 8, 2012Applicant: Fujitsu LimitedInventors: Youji UCHIKURA, Akiyoshi Saitou, Yukihiko Onishi, Manabu Nakagawa
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Publication number: 20110208485Abstract: A bonding surface extraction unit extracts, with reference to bonding information, data of a first bonding surface corresponding to a bottom surface of a bonding model from data of a first partial model and data of a second bonding surface corresponding to a top surface of the bonding model from data of a second partial model. The first partial model is a model of a pad included in a circuit board. The second partial model is a model of an electrode included in a component. The electrode is to be bonded to the pad with a bonding material. A bonding model generation unit generates a side surface establishing a link between outlines of the first bonding surface and the second bonding surface, and obtains data of the bonding model on the basis of a shape formed with the side surface, the first bonding surface, and the second bonding surface.Type: ApplicationFiled: February 9, 2011Publication date: August 25, 2011Applicant: FUJITSU LIMITEDInventors: Nobutaka ITOH, Makoto Sakairi, Mami Nakadate, Yoshiteru Ochi, Akiyoshi Saitou
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Publication number: 20100288545Abstract: A printed wiring board having an insulating core; a plurality of vias having axes parallel to and at equal distance from a reference axis and passing through the core; a first conductive film formed on a front surface of the core from the reference axis to each of the individual vias; a first insulating film stacked on the front surface of the core and covering the first conductive film; a first connecting via having an axis identical to the reference axis and passing through the first stacked film; a second conductive film formed on a back surface of the core from the reference axis to each of the individual vias; a second insulating film stacked on the back surface of the core and covering the second conductive film; and a second connecting via having an axis identical to the reference axis and passing through the second stacked film.Type: ApplicationFiled: May 7, 2010Publication date: November 18, 2010Applicant: FUJITSU LIMITEDInventor: Akiyoshi Saitou
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Publication number: 20070295533Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.Type: ApplicationFiled: June 1, 2007Publication date: December 27, 2007Applicant: FUJITSU LIMITEDInventors: Akiyoshi Saitou, Takeshi Midorikawa, Toru Kuraishi, Chikayuki Kumagai, Masashi Fujimoto, Kenichiro Abe
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Patent number: 7304858Abstract: A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.Type: GrantFiled: December 29, 2004Date of Patent: December 4, 2007Assignee: Fujitsu LimitedInventor: Akiyoshi Saitou
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Publication number: 20070144773Abstract: The present invention relates to a circuit board in which signal lines transmitting a signal are wired, and which is capable of increasing the speed of signal transmission. There is provided a circuit board in which signal lines are wired, including: a signal pad which is formed at the tip of the signal line and has a signal via in the center thereof; and plural ground vias which are formed in positions to surround the signal pad and transmit a ground potential over plural wiring layers.Type: ApplicationFiled: March 27, 2006Publication date: June 28, 2007Applicant: FUJITSU LIMITEDInventors: Akiyoshi Saitou, Toru Kuraishi, Takeshi Midorikawa, Chikayuki Kumagai, Masashi Fujimoto
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Publication number: 20060057889Abstract: A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.Type: ApplicationFiled: December 29, 2004Publication date: March 16, 2006Applicant: FUJITSU LIMITEDInventor: Akiyoshi Saitou