Patents by Inventor Akiyoshi Sawai
Akiyoshi Sawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11311970Abstract: A shielding gas nozzle for metal forming includes a wire feed line being a path to feed a wire at an inclination angle ?, a first gas ejection hole to jet a shielding gas at an angle equal to or less than the inclination angle ?, and a second gas ejection hole to jet the shielding gas in a direction different from that of the first gas ejection hole. The first gas ejection hole jets the shielding gas toward an intersection along a direction in which the absolute value of the angle to the wire feed direction is less than 90 degrees, and the second gas ejection hole jets the shielding gas toward the intersection along a direction in which the absolute value of the angle to the wire feed direction when viewed in the direction perpendicular to the base material surface is greater than 90 degrees.Type: GrantFiled: April 16, 2019Date of Patent: April 26, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshikazu Nakano, Hidetaka Katogi, Akiyoshi Sawai
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Publication number: 20220088712Abstract: A shielding gas nozzle for metal forming includes a wire feed line being a path to feed a wire at an inclination angle ?, a first gas ejection hole to jet a shielding gas at an angle equal to or less than the inclination angle ?, and a second gas ejection hole to jet the shielding gas in a direction different from that of the first gas ejection hole. The first gas ejection hole jets the shielding gas toward an intersection along a direction in which the absolute value of the angle to the wire feed direction is less than 90 degrees, and the second gas ejection hole jets the shielding gas toward the intersection along a direction in which the absolute value of the angle to the wire feed direction when viewed in the direction perpendicular to the base material surface is greater than 90 degrees.Type: ApplicationFiled: April 16, 2019Publication date: March 24, 2022Applicant: Mitsubishi Electric CorporationInventors: Yoshikazu NAKANO, Hidetaka KATOGI, Akiyoshi SAWAI
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Patent number: 6457876Abstract: A surface-mountable optical device has an optical component unit and an receptacle unit. The optical component unit has a package, inner optical components installed in the package, a plurality of surface-mountable leads protruded from the package, and a ferrule optically coupled to the inner optical components and protruded from the package in a predetermined direction. The receptacle unit has a receptacle for holding an optical fiber cable to ensure an optical coupling between the optical fiber cable and the ferrule, and a plurality of surface-mountable leads fixed on the receptacle. The surface-mountable optical device and the receptacle unit are provided independently, and also the receptacle unit is inserted into the surface-mountable optical unit along the predetermined direction.Type: GrantFiled: March 10, 2000Date of Patent: October 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akiyoshi Sawai
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Patent number: 6451622Abstract: An optical device and a method for manufacturing the optical device. An optical device having a molded-package structure includes: a lead frame having a ferrule-mounting portion; a ferrule mounted on the ferrule-mounting portion; and a molding resin that encapsulates the lead frame and the ferrule, molding, except that an end of the ferrule protrudes through and outside of the surface of the molding resin. The first groove parallel to a longitudinal axis of the ferrule is located on the ferrule-mounting portion and the ferrule is placed on the first groove. Thus, the ferrule is hardly ever detached from a ferrule-mounting portion, an optical fiber is hardly ever damaged, and an optical coupling is hardly ever obstructed.Type: GrantFiled: April 26, 2000Date of Patent: September 17, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akiyoshi Sawai
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Patent number: 6256875Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.Type: GrantFiled: September 22, 1999Date of Patent: July 10, 2001Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
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Patent number: 6177724Abstract: A semiconductor package has a first region having a thickness equivalent to or slightly larger than a semiconductor chip 4 (0.35 to 0.7 mm) and sealed with resin, and a second region provided on the outside of the first region, having a thickness smaller than that of the first region (0.15 mm to 0.35 mm), and sealed with resin. A semiconductor having a mold package structure capable of preventing the package from warpage can be provided according to this structure.Type: GrantFiled: September 16, 1999Date of Patent: January 23, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Akiyoshi Sawai
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Patent number: 6046071Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.Type: GrantFiled: November 24, 1997Date of Patent: April 4, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
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Patent number: 6005289Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.Type: GrantFiled: October 24, 1996Date of Patent: December 21, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
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Patent number: 5903048Abstract: A lead frame including a holding portion having an area smaller than a semiconductor element to be mounted on the holding portion; and a suspension lead extending outward from the holding portion, from opposite sides of the holding portion, for supporting the holding portion.Type: GrantFiled: May 20, 1997Date of Patent: May 11, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kouji Bandou, Akiyoshi Sawai, Hideki Hukunaga
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Patent number: 5834340Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.Type: GrantFiled: November 24, 1997Date of Patent: November 10, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
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Patent number: 5814883Abstract: A semiconductor device includes a substrate having a recess; a semiconductor chip disposed in the recess; a plurality of external electrodes disposed on the substrate; a lid covering the recess; and a heat radiator disposed between the semiconductor chip and the substrate for transmitting heat generated by the semiconductor chip to the substrate for radiation.Type: GrantFiled: May 1, 1996Date of Patent: September 29, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Eengineering CorporationInventors: Akiyoshi Sawai, Kisamitsu Ono, Hideyuki Ichiyama, Katsunori Asai
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Patent number: 5710062Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.Type: GrantFiled: June 1, 1995Date of Patent: January 20, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata
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Patent number: 5666008Abstract: A semiconductor device for life enhancement of electrical connections between a semiconductor chip and a mounting substrate. Protruding electrodes, each including a bump electrode and a land electrode, are located on the lower surface of an LSI chip. The bump electrodes are substantially spherical and have a first thickness. Connecting terminals of substantially spherical configuration and having a second thickness are directly connected to corresponding land electrodes by melting. Connecting patterns are located on the upper surface of a wiring board which is larger in area than the LSI chip in plan configuration, and external electrodes, each including a connecting pattern and an external electrode, are located on the lower surface of the wiring board. The external electrodes are substantially spherical and have a third thickness. The connecting patterns are directly connected to corresponding connecting terminals, respectively, by melting.Type: GrantFiled: September 6, 1996Date of Patent: September 9, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Yoshihiro Tomita, Akiyoshi Sawai, Katsunori Asai
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Patent number: 5554887Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.Type: GrantFiled: April 28, 1994Date of Patent: September 10, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akiyoshi Sawai, Haruo Shimamoto, Toru Tachikawa, Jun Shibata