Patents by Inventor Akiyuki Hatakeyama

Akiyuki Hatakeyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070180249
    Abstract: Methods and apparatus provide for: requiring that a content provider seeking to have its content executed by a processing system enter into an accord with a processing system provider; receiving a second key and a digital signature from the content provider to the processing system provider, the second key being operable to decrypt the content when it has been encrypted with a first key, and the digital signature indicating that the accord has been reached; receiving the encrypted content from the content provider in a memory of the processing system; and preventing use of one or more processing resources of the processing system that are otherwise operable to facilitate the execution of the content unless the digital signature is received from the processing system provider.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 2, 2007
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20070176625
    Abstract: Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.
    Type: Application
    Filed: January 8, 2007
    Publication date: August 2, 2007
    Applicant: SONY COMPUTER ENTERTAINMENT INC.
    Inventors: Atsushi Hayashi, Akiyuki Hatakeyama, Taichi Niki, Yoichi Nishino
  • Publication number: 20060245588
    Abstract: Methods and apparatus provide for: dividing a quantity of data values into a plurality of blocks; dividing the plurality of blocks into respective sub-sets of blocks; computing an intermediate message authentication code block for each sub-set of blocks by performing a first cipher block chaining algorithm on the blocks of each sub-set of blocks; and computing a message authentication code block for the plurality of blocks by performing a second cipher block chaining algorithm on the intermediate message authentication code blocks.
    Type: Application
    Filed: February 3, 2006
    Publication date: November 2, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060212680
    Abstract: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.
    Type: Application
    Filed: January 31, 2006
    Publication date: September 21, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Masahiro Yasue, Akiyuki Hatakeyama
  • Publication number: 20060190733
    Abstract: Methods and apparatus provide for receiving encrypted content including program code, data, and a digital signature in a memory of a processing system, the content being encrypted using a first key; decrypting the encrypted content using a second key stored locally within the processing system; retrieving the digital signature from the content and verifying its authenticity; and permitting use of one or more processing resources that are operable to facilitate the execution of the program code by a processor of the processing system if the digital signature is authentic.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 24, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060179302
    Abstract: Methods and apparatus provide for: reading encrypted boot code from a storage medium into a local memory associated with a first of a plurality of processors; decrypting the encrypted boot code using a trusted decryption function of the first processor such that the boot code is verified as being authentic; booting the first processor using the boot code from the local memory; and authenticating boot code for one or more of the other processors in the first processor prior to the one or more other processors booting up.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060179324
    Abstract: Methods and apparatus provide for verifying operating system software integrity prior to being executed by a processor, the processor including an associated local memory and capable of operative connection to a main memory such that data may be read from the main memory for use in the local memory; storing a status flag indicating whether the operating system software integrity is or is not satisfactory; and ensuring that the status flag indicates that the operating system software integrity is satisfactory before permitting the processor to continue in a course of action.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060179487
    Abstract: In a multi-processor system including a plurality of processors capable of being operatively coupled to the main memory and each processor including an associated local memory, and at least one main processor operable to control access by the processors to data within the main memory and within the processors, methods and apparatus provide for: entering a secure mode of operation within at least one of the processors in which no requests initiated by others of the processors for data transfers into or out of the at least one processor are serviced, but such transfers initiated by the at least one processor are serviced subject to the access controlled by the main processing unit; and using the main processing unit to exclude access to data associated with at least one further processor by others of the processors except for the at least one processor.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060177068
    Abstract: A processor and associated local memory are capable of operative connection to a main memory such that data may be read from the main memory for use in the local memory, and the processor is operable to carry out actions, including: entering a secure mode of operation where externally initiated requests to read data from or write data into the processor are not serviced but internally initiated data transfers are serviced; reading a decryption program from a storage medium into the local memory of the processor; reading an encrypted authentication program into the local memory of the processor; decrypting the encrypted authentication program using a decryption program; and transitioning functionality of the processor from the decryption program to the authentication program.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Applicant: Sony Computer Entertainment Inc.
    Inventor: Akiyuki Hatakeyama
  • Publication number: 20060112213
    Abstract: Methods and apparatus for placing a processing unit into one or more of a plurality of operational modes are disclosed wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes a first mode whereby the apparatus and an external device may initiate a transfer of information into or out of the memory over the bus, a second mode whereby neither the apparatus nor the external device may initiate a transfer of information into or out of the memory over the bus, and a third mode whereby the apparatus may initiate a transfer of information into or out of the memory over the bus, but the external device may not initiate a transfer of information into or out of the memory over the bus.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 25, 2006
    Inventors: Masakazu Suzuoki, Akiyuki Hatakeyama
  • Patent number: 6948072
    Abstract: An information processing device to solve the above-mentioned disadvantage according to the present invention comprises: information receipt part to receive a digital information from an external information record medium; first judgment part to judge whether the external information record medium is a medium which is readable and writable; second judgment part which judges whether a predetermined security processing is performed to the digital information to be received; and control part to control the information receipt part to refuse a receipt of the digital information which is judged that the medium is readable and writable by the first judgment part and a security processing is not performed by the second judgment part.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 20, 2005
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Akiyuki Hatakeyama, Keiso Shimakawa, Tadayasu Hakamatani, Makoto Tanaka
  • Publication number: 20010024503
    Abstract: The entertainment apparatus comprises a main bus and a subbus, which are connected to each other via a center bus having a queue. A CPU, a memory, an image processor and a DMAC are connected to the main bus. A disk drive, an I/O processor, a sound processor, and a security module are connected to the subbus. A program code, which is compressed and partially encrypted, is recorded on a secondary recording medium. The I/O processor obtains a decryption key from the security module. The I/O processor decrypts digital information read from the secondary recording medium based on the decryption key and decompresses the digital information. The decompressed digital information is written into the memory via the queue using a DMA transfer.
    Type: Application
    Filed: March 1, 2001
    Publication date: September 27, 2001
    Inventors: Akiyuki Hatakeyama, Tsutomu Horikawa
  • Publication number: 20010020256
    Abstract: An information processing device to solve the above-mentioned disadvantage according to the present invention comprises: information receipt part to receive a digital information from an external information record medium; first judgment part to judge whether the external information record medium is a medium which is readable and writable; second judgment part which judges whether a predetermined security processing is performed to the digital information to be received; and control part to control the information receipt part to refuse a receipt of the digital information which is judged that the medium is readable and writable by the first judgment part and a security processing is not performed by the second judgment part.
    Type: Application
    Filed: March 1, 2001
    Publication date: September 6, 2001
    Inventors: Akiyuki Hatakeyama, Keiso Shimakawa, Tadayasu Hakamatani, Makoto Tanaka