Patents by Inventor Akm Shaestagir CHOWDHURY

Akm Shaestagir CHOWDHURY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006628
    Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Leonard P. GULER, Vishal TIWARI, Akm Shaestagir CHOWDHURY, Charles H. WALLACE
  • Publication number: 20230420361
    Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Nita CHANDRASEKHAR, Vishal TIWARI, AKM Shaestagir CHOWDHURY
  • Publication number: 20230101107
    Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: AKM Shaestagir CHOWDHURY, Debashish BASU, Githin F. ALAPATT, Justin E. MUELLER, James Y. JEONG
  • Publication number: 20220093514
    Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Nita CHANDRASEKHAR, AKM Shaestagir CHOWDHURY
  • Publication number: 20220059467
    Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Applicant: Intel Corporation
    Inventors: Yang CAO, Akm Shaestagir CHOWDHURY, Jeff GRUNES
  • Publication number: 20210305161
    Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Nita CHANDRASEKHAR, AKM Shaestagir CHOWDHURY
  • Publication number: 20170018506
    Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 19, 2017
    Applicant: Intel Corporation
    Inventors: Yang CAO, Akm Shaestagir CHOWDHURY, Jeff GRUNES