Patents by Inventor Ako Hatano

Ako Hatano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5998810
    Abstract: A semiconductor light-emitting diode exhibiting an oscillation wavelength of 450 nm or less and comprising a substrate, a lower clad layer formed on or above the substrate and mainly composed of a III-V Group compound semiconductor, an active layer formed directly on the lower clad layer and mainly composed of a III-V Group compound semiconductor, and an upper p-type clad layer formed directly on the active layer and mainly composed of a III-V Group compound semiconductor. This semiconductor light-emitting diode is characterized in that the upper p-type clad layer contains Mg, Si and at least one impurities for compensating residual donors.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Yasuo Ohba, Hidetoshi Fujimoto, Kazuhiko Itaya, Johji Nishio
  • Patent number: 5929466
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1) and is formed on a surface of the substrate such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. A method of fabricating a semiconductor device comprises the steps of: forming, above an Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano
  • Patent number: 5909040
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1) and formed on a surface of the substrate with an average film thickness of 5 nm to 20 nm such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. The pinholes are formed among loosely formed small crystals of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1).
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: June 1, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano
  • Patent number: 5740192
    Abstract: A semiconductor laser exhibiting an oscillation wavelength of 450 nm or less and comprising a substrate, a lower clad layer formed on or above the substrate and mainly composed of a III-V Group compound semiconductor, an active layer formed directly on the lower clad layer and mainly composed of a III-V Group compound semiconductor, and an upper p-type clad layer formed directly on the active layer and mainly composed of a III-V Group compound semiconductor. This semiconductor laser is characterized in that the upper p-type clad layer contains Mg, Si and at least one impurities for compensating residual donors.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: April 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Yasuo Ohba, Hidetoshi Fujimoto, Kazuhiko Itaya, Johji Nishio
  • Patent number: 5656832
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s .ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1) and is formed on a surface of the substrate such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. A method of fabricating a semiconductor device comprises the steps of: forming, above an Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: August 12, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano
  • Patent number: 5617438
    Abstract: A semiconductor laser having an oscillation wavelength of not more than 450 nm comprises a substrate, a lower cladding layer containing a III-V Group compound semiconductor as a main component formed on the substrate, an active layer containing the III-V Group compound semiconductor as a main component formed on the lower cladding layer and an upper p-type cladding layer containing III-V Group compound semiconductor as a main component. Mg and Si are contained in the upper p-type cladding layer. A GaN series compound semiconductor is preferably used as the III-V Group compound semiconductor and the upper cladding layer contains preferably not less than 5.times.10.sup.18 /cm.sup.3 of Si.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: April 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Yasuo Ohba
  • Patent number: 5432808
    Abstract: A compound semiconductor light-emitting device includes a cubic SiC substrate, and an Ga.sub.x Al.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) layer formed on the (111) surface of the cubic-crystal SiC substrate. The surface of the Ga.sub.x Al.sub.y In.sub.1-x-y N layer, which opposes the substrate, is an N surface, and the light-emitting device has a pn junction.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: July 11, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Yasuo Ohba
  • Patent number: 5317167
    Abstract: A semiconductor light-emitting device comprises a light-emitting layer including a pn junction formed by a plurality of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x, y.ltoreq.1) layers, and a light-emitting-layer holding layer consisting of an indirect transition type Ga.sub.1-w Al.sub.w As (0.ltoreq.w.ltoreq.1) provided on an opposite side to a light-outputting side. The holding layer has a sufficiently small light absorption coefficient for the light from the light-emitting layer although its band gap is small and improves the light emission efficiency of the semiconductor light-emitting device.
    Type: Grant
    Filed: May 10, 1993
    Date of Patent: May 31, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Izumiya, Yasuo Ohba, Ako Hatano
  • Patent number: 5273933
    Abstract: In a process of manufacturing a short-wavelength-light emitting element, n- and p-type GaInAlN films are formed on a substrate made of SiC, using an MOCVD method. (CH.sub.3).sub.3 SiN.sub.3 is used as raw material for nitrogen. The films are grown at a relatively low temperature and the amount of nitrogen doped in the films is increased.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: December 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Toshihide Izumiya, Yasuo Ohba
  • Patent number: 5235194
    Abstract: A semiconductor light-emitting device comprises a light-emitting layer including a pn junction formed by a plurality of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x, y.ltoreq.1) layers, and a light-emitting-layer holding layer consisting of an indirect transition type Ga.sub.l-w Al.sub.w As (0.ltoreq.w.ltoreq.1) provided on an opposite side to a light-outputting side. The holding layer has a sufficiently small light absorption coefficient for the light from the light-emitting layer although its band gap is small and improves the light emission efficiency of the semiconductor light-emitting device.
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: August 10, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Izumiya, Yasuo Ohba, Ako Hatano
  • Patent number: 5103271
    Abstract: A semiconductor light-emitting device comprises a light-emitting layer including a pn junction formed by a plurality of In.sub.x Ga.sub.y Al.sub.l-x-y P (0.ltoreq.x, y.ltoreq.l) layers, and a light-emitting-layer holding layer consisting of an indirect transition type Ga.sub.l-w Al.sub.w As (0.ltoreq.w.ltoreq.l) provided on an opposite side to a light-outputting side. The holding layer has a sufficiently small light absorption coefficient for the light from the light-emitting layer even though its band gap is small and improves the light emission efficiency of the semiconductor light-emitting device.
    Type: Grant
    Filed: September 27, 1990
    Date of Patent: April 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Izumiya, Yasuo Ohba, Ako Hatano
  • Patent number: 5079184
    Abstract: A magnesium-doped p-type III-V Group compound semiconductor layer can be formed by metal organic chemical vapor deposition, by reacting, in a vapor phase, at least one compound of a Group III element with at least one compound of a Group V element, in the presence of an adduct of an organic magnesium compound with another compound as a doping source of magnesium.
    Type: Grant
    Filed: June 15, 1990
    Date of Patent: January 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Toshihide Izumiya, Yasuo Ohba
  • Patent number: 5076860
    Abstract: A compound semiconductor material includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) containing B and P and having a zinc blend type crystal structure. A compound semiconductor element includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer having a zinc blend type crystal structure. A method of manufacturing a compound semiconductor element includes the step of sequentially forming a BP layer and a Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer on a substrate so as to form a heterojunction by using a metal organic chemical vapor deposition apparatus having a plurality of reaction regions, and moving the substrate between the plurality of reaction regions.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: December 31, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Toshihide Izumiya, Ako Hatano
  • Patent number: 5042043
    Abstract: A green light-emitting semiconductor laser using a superlattice layer wherein BP layers and Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers are alternately stacked and each of the Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers has a zinc blende type crystal structure, or a Ga.sub.x Al.sub.y B.sub.1-x-y N.sub.z P.sub.1-z (0.ltoreq.x, y, z.ltoreq.1) mixed crystal layers with a zinc blende type structure a first clad layer of a first conductivity type, an active layer, and a second clad layer of a second conductivity type, together constituting a double heterojunction.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: August 20, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Toshihide Izumiya, Yasuo Ohba
  • Patent number: 5005057
    Abstract: A blue LED which includes a light-emitting layer having a p-n junction makes use of the superlattice structure being formed of a plurality of BP layers and Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers which are alternately stacked, with the Ga.sub.x Al.sub.1-x N (0.ltoreq.x.ltoreq.1) layers having a zinc blende type structure, or else makes use of a Ga.sub.x Al.sub.y B.sub.1-x-y N.sub.z P.sub.1-z (0.ltoreq.x, y, z.ltoreq.1 and x+y.ltoreq.1) mixed crystal layer having a zinc blende type crystal structure.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: April 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Izumiya, Yasuo Ohba, Ako Hatano
  • Patent number: RE38805
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al1-x-yGaxInyN (0?x?1, 0?y?1, x+y?1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al1-s-tGasIntN (0?s?1, 0?t?1, s+t?1) and is formed on a surface of the substrate such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. A method of fabricating a semiconductor device comprises the steps of: forming, above an Al1-x-yGaxInyN (0?x?1, 0?y?1, x+y?1) semiconductor layer doped with a p-type dopant, a cap layer for preventing evaporation of a constituent element of the semiconductor layer, the cap layer being formed of one of AlN in which a p-type dopant is added and Al2O3, subjecting the semiconductor layer to heat treatment, and removing at least a part of the cap layer.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: October 4, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano