Patents by Inventor Akram Ali Salman

Akram Ali Salman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210408270
    Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Inventors: Zaichen Chen, Akram Ali Salman
  • Patent number: 10978443
    Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 13, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Akram Ali Salman, Jun Cai, Krishna Praveen Mysore Rajagopal
  • Publication number: 20210005599
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Publication number: 20200388606
    Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Akram Ali Salman, Jun Cai, Krishna Praveen Mysore Rajagopal
  • Publication number: 20200328204
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Patent number: 10784251
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Patent number: 10700055
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 30, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Publication number: 20200203333
    Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first conductivity type and a transistor formed within the substrate that includes a buried layer having a second conductivity type. A first doped region, located between the buried layer and a surface of the substrate, has the first conductivity type and a second doped region, extending from the substrate surface to the buried layer, has the second conductivity type. A third doped region, located between the buried layer and the surface and between the first doped region and the second doped region, has the second conductivity type and a first dopant concentration. A fourth doped region, located between the third doped region and the substrate surface and between the first doped region and the second doped region, has a second dopant concentration less than the first dopant concentration. A method of fabricating the IC is also shown.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Zaichen Chen, Akram Ali Salman
  • Publication number: 20190229111
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Publication number: 20190181134
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Patent number: 10249607
    Abstract: An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an upper emitter. The lower NPN includes a lower collector, a lower base, and a lower emitter. The upper collector includes collector segments on opposite sides of the lower emitter. The collector segments are laterally separated by collector separators which are aligned to orientation directions in the collector segments. The upper collector does not have collector separators across the orientation directions.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Patent number: 7205165
    Abstract: The present invention is generally directed to various methods for determining the reliability of dielectric layers. In one illustrative embodiment, the method comprises providing a device having a dielectric layer, applying a plurality of constant voltage pulses to the device and measuring a current through the dielectric layer after one or more of the constant voltage pulses has been applied.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: April 17, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Akram Ali Salman, Xuejun Zhao, Kurt O. Taylor, Stephen G. Beebe