Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

Abstract: A computer chip, such as an System on chip (SOC), can receive firmware updates having two separate signatures; a first of the signatures is used to authenticate the firmware using a processor within the computer chip, and a second of the signatures is used by a controller, separate from the processor. A first key, used by the processor to authenticate the firmware, can be a boot key that is hardwired in the computer chip. A second key, used by the controller, can be a key that is provided to the controller at any time and is updatable. The controller can suspend the processor so that the controller can perform a first authentication of the firmware using the second signature and the second key. If the authentication is successful, the controller can release the processor, which then uses the first key and the first signature to perform a second authentication.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: To verify hardware, identical input values are provided to the first device under test and to the second device under test where the second device under test is logically identical to the first device under test. Output values of the first device under test and the second device under test are compared where both first output values from the first device under test are deterministically predictable from the identical input values and where second output values from the second device under test are deterministically predictable from the identical input values. Differences in the first output values from the second output values indicate incorrect operation.

Abstract: A method for verification of hardware uses self-equivalence to leverage automated abstractions where data path elements are identical in two designs. Equivalence is used between a qualified design and an independent reference.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.