Abstract: A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) array of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+moat). A first portion of the n+moats are collector (C) units, and a second portion of the n+moats are emitter (E) units. Each of the E units is separated from a nearest neighbor E unit by a C unit.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.

Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Abstract: A circuit and method for electrostatic discharge testing using transmission line pulsing. A plurality of transmission line networks may be connected to a device under test, and each transmission line network may have different connected terminations. Switches may be used to select which transmission line networks are connected to the device under test, and which terminations, if any, are connected to transmission line networks.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.

Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.