Abstract: Systems, methods, and other embodiments associated with cyclic redundancy checking for wide data busses are described. According to one embodiment, a method comprises, in response to detecting a data block on a data bus, identifying a data lane of the data bus on which the data block begins and initializing a starting processing unit of a series of processing units. The starting processing unit corresponds with the identified data lane by issuing a mask input to prior processing units that are ahead of the starting processing unit within the series. Issuing the mask input causes the prior processing units to feed a seed value to the starting processing unit. A cyclic redundancy check value is generated for the data block by initiating the generating from the starting processing unit and iteratively cycling through the series of processing units until the block of data is completed.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.