Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: A power management system permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off. The power management system supports asynchronous domains with common shared peripherals. The asynchronous domains operate as a single entity while in a full power mode with the peripheral and system resources being shared. The system can be used in automotive systems where most of the system is power-gated leaving just a power regulator controller, some counters and an input/output segment alive for wakeup purposes.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.

Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.