Patents by Inventor Akshay Mathkar

Akshay Mathkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586779
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Patent number: 9941652
    Abstract: Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar, Dingying Xu
  • Publication number: 20180047693
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Nachiket R. RARAVIKAR, James C. MATAYABAS, JR., Akshay MATHKAR
  • Patent number: 9831206
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr., Akshay Mathkar
  • Publication number: 20170176496
    Abstract: Prober space transformer to interface an E-testing apparatus to an unpackaged die. The space transformer may include a substrate and a perforated cover plate disposed on the substrate. The substrate may include conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as a prober interface between an E-testing apparatus and a DUT. The cover plate may be affixed to a surface of the substrate and includes an array of perforations through which the array of conductive pins may pass. The cover plate may be synthetic polymer resin or a polymer-based composite, fabricated, for example by perforating a mold preform.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Akshay Mathkar, Nachiket R. Raravikar, James C. Matayabas, Jr., Jin Yang
  • Publication number: 20170179080
    Abstract: Semiconductor package interposers having high-density and high-aspect ratio encapsulated interconnects, and semiconductor package assemblies incorporating such interposers, are described. In an example, a semiconductor package interposer includes several conductive interconnects encapsulated in a polymer substrate and having height dimensions greater than a cross-sectional dimension. The semiconductor package interposer may support a first semiconductor package above a second semiconductor package and may electrically connect die pins of the first semiconductor package to die pins of the second semiconductor package.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Akshay MATHKAR, Nachiket Raghunath RARAVIKAR, Donald Tiendung TRAN, Jerry Lee JENSEN, Javier A. FALCON, William Nicholas LABANOK, Robert Leon SANKMAN, Robert Allen STINGEL
  • Publication number: 20170176518
    Abstract: Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Nachiket R. Raravikar, James C. Matayabas, JR., Akshay Mathkar, Dingying Xu
  • Publication number: 20150279804
    Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Nachiket R. RARAVIKAR, James C.j Matayabas, Akshay Mathkar
  • Publication number: 20150027615
    Abstract: The present invention provides additive manufacturing methods of forming multilayer energy storage devices on a surface by formulating all components of the multilayer energy storage device into liquid compositions and: (1) applying a first liquid current collector composition above the surface to form a first current collector layer above the surface; (2) applying a first liquid electrode composition above the first current collector layer to form a first electrode layer above the first current collector layer; (3) applying a liquid electrically insulating composition above the first electrode layer to form an electrically insulating layer above the first electrode layer; (4) applying a second liquid electrode composition above the electrically insulating layer to form a second electrode layer above the electrically insulating layer; and (5) applying a second liquid current collector composition above the second electrode layer to form a second current collector layer above the second electrode layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 29, 2015
    Applicant: William Marsh Rice University
    Inventors: Neelam Singh, Charudatta Galande, Akshay Mathkar, Leela M. Reedy Arava, Pulickel M. Ajayan, Alexandru Vlad