Abstract: A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to reduce post-buffer power/delay cost for a spanning tree. The system and method may prune Hanan points prior to calling a buffering tool to insert buffers and insert non-Hanan branching points. Embodiments may also include dividing a device into a plurality of super unit blocks, performing routing within each of the plurality of super units using a single crossing Steiner tree algorithm to determine a corresponding port, and aligning corresponding ports of each super unit to provide routing between the plurality of super units.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location can be determined.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined.

Abstract: Implementations of the present disclosure involve methods and systems for component placement in a datapath block of a microelectronic circuit design. In particular, implementations provide for collecting groups of common components in the datapath block that form a row or partial row. A preliminary layout of the datapath block is performed with the component set rows and any other components of the datapath block design. Common components are then collected into groups or sets to form additional rows within the datapath layout, with at least some consideration to the wire lengths between components in the rows. By collecting common components into rows with consideration to the wire lengths between interconnected components, the timing performance of the datapath block may be improved.

Abstract: Implementations of the present disclosure involve methods and systems for component placement in a datapath block of a microelectronic circuit design. In particular, implementations provide for collecting groups of common components in the datapath block that form a row or partial row. A preliminary layout of the datapath block is performed with the component set rows and any other components of the datapath block design. Common components are then collected into groups or sets to form additional rows within the datapath layout, with at least some consideration to the wire lengths between components in the rows. By collecting common components into rows with consideration to the wire lengths between interconnected components, the timing performance of the datapath block may be improved.

Abstract: A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to reduce post-buffer power/delay cost for a spanning tree. The system and method may prune Hanan points prior to calling a buffering tool to insert buffers and insert non-Hanan branching points. Embodiments may also include dividing a device into a plurality of super unit blocks, performing routing within each of the plurality of super units using a single crossing Steiner tree algorithm to determine a corresponding port, and aligning corresponding ports of each super unit to provide routing between the plurality of super units.