Abstract: A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.

Abstract: A data processing system comprising a plurality of processing units that are configurable as different partitions of processing units. The system comprises a multicast communication network for routing cache communications within a partition of processing unit. A cache controller of one of the processing units within a partition is configurable as a master cache controller for a set of caches within the partition. The master cache controller is operable to issue requests over the multicast communication network to all of the caches in the set of caches at the same time. The multicast communication network is configured to combine response signals from the different processing units within the partition to provide a combined response signal to the master cache controller that represents an overall request-response status for the caches to which the request was issued.

Abstract: In a data processing system in which varying numbers of channels for accessing a memory can be configured, the communications channel to use for an access to the memory is determined by mapping a memory address associated with the memory access to an intermediate address within an intermediate address space, selecting, based on the number of channels configured for use to access the memory, a mapping operation to use to determine from the intermediate address which channel to use for the memory access, and using the selected mapping operation to determine from the intermediate address which channel to use for the memory access.

Abstract: A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.

Abstract: A data processing system comprising a plurality of processing units that are configurable as different partitions of processing units. The system comprises a multicast communication network for routing cache communications within a partition of processing unit. A cache controller of one of the processing units within a partition is configurable as a master cache controller for a set of caches within the partition. The master cache controller is operable to issue requests over the multicast communication network to all of the caches in the set of caches at the same time. The multicast communication network is configured to combine response signals from the different processing units within the partition to provide a combined response signal to the master cache controller that represents an overall request-response status for the caches to which the request was issued.