Abstract: Example embodiments relate to transmitter-receiver leakage suppression in integrated radar systems. One embodiment includes a front-end for a radar system. The front-end includes a transmit path that includes a power amplifier and a transmit antenna. The transmit path is configured to transmit a transmit signal. The front-end also includes a receive path that includes a receive antenna and a low-noise amplifier. The receive path is configured to receive at least a leakage from the transmit path. The receive path is configured to generate an amplified signal of the leakage. Further, the front-end also includes a reference path. In addition, the front-end includes a compensation unit in the reference path. The compensation unit is configured to generate compensation for a leakage path between the transmit path and the receive path. The compensation unit is configured to apply the generated compensation to the reference signal to generate a compensated reference signal.

Abstract: A multi-chip system is configured as an antenna array. The multi-chip system includes at least two transmitting sets distributed over one or more transmitting chips, where the transmitting sets each include an integrated transmitting antenna and an integrated up-conversion circuit. The multi-chip system further includes at least two receiving chips, where the receiving chips each include at least one integrated receiving antenna and at least one integrated down-conversion circuit.

Abstract: Example embodiments relate to transmitter-receiver leakage suppression in integrated radar systems. One embodiment includes a front-end for a radar system. The front-end includes a transmit path that includes a power amplifier and a transmit antenna. The transmit path is configured to transmit a transmit signal. The front-end also includes a receive path that includes a receive antenna and a low-noise amplifier. The receive path is configured to receive at least a leakage from the transmit path. The receive path is configured to generate an amplified signal of the leakage. Further, the front-end also includes a reference path. In addition, the front-end includes a compensation unit in the reference path. The compensation unit is configured to generate compensation for a leakage path between the transmit path and the receive path. The compensation unit is configured to apply the generated compensation to the reference signal to generate a compensated reference signal.

Abstract: A multi-chip system is configured as an antenna array. The multi-chip system includes at least two transmitting sets distributed over one or more transmitting chips, where the transmitting sets each include an integrated transmitting antenna and an integrated up-conversion circuit. The multi-chip system further includes at least two receiving chips, where the receiving chips each include at least one integrated receiving antenna and at least one integrated down-conversion circuit.

Abstract: A novel and useful wideband FM demodulator operating across an 8 GHz IF bandwidth for application in low-power, wideband heterodyne receivers. The demodulator includes an n-stage ring oscillator that is injection locked to a wideband input signal. Locking to the input frequency, it divides the FM deviation by n, thereby facilitating as well as reducing the energy required for wideband demodulation. The quadrature-phased output of the ring oscillator is phase correlated using a low-power folded CMOS mixer capable of detecting FM up to 400 Mb/s over a 2-10 GHz IF frequency range.

Abstract: A novel and useful wideband FM demodulator operating across an 8 GHz IF bandwidth for application in low-power, wideband heterodyne receivers. The demodulator includes an n-stage ring oscillator that is injection locked to a wideband input signal. Locking to the input frequency, it divides the FM deviation by n, thereby facilitating as well as reducing the energy required for wideband demodulation. The quadrature-phased output of the ring oscillator is auto correlated using a low-power folded CMOS mixer capable of detecting FM up to 400 Mb/s over a 2-10 GHz IF frequency range.

Abstract: The invention relates to an oscillator circuit, comprising a clipping element for generating a clipped signal, and a first amplification stage for amplifying and filtering the clipped signal to obtain a filtered signal, wherein the clipping element is configured to generate the clipped signal upon the basis of the filtered signal.