Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

Abstract: Technologies for air gaps in semiconductor dies with aluminum oxide liners are disclosed. In an illustrative embodiment, high-aspect-ratio traces on an interconnect layer of a semiconductor die have a relatively narrow pitch. In order to reduce the capacitance between neighboring traces, an air gap is present. A liner above the air gap prevents the air gap from being filled during the semiconductor processing. In an illustrative embodiment, the liner is aluminum oxide, which may prevent stress induced leakage current (SILC) that may result when using silicon oxide or other materials.

Abstract: An apparatus comprising an integrated circuit die comprising a first interconnect layer; a second interconnect layer; and a plurality of vias coupling the first interconnect layer to the second interconnect layer; wherein the first interconnect layer comprises a conductive material having a grain size of at least 100 nanometers.

Abstract: An integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. The integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. An opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. The second interconnect feature extends through the opening. In an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). In an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.

Abstract: In a metallization layer of an integrated circuit device, air gaps are formed between adjacent metal lines, e.g., between high aspect ratio metal lines at tight pitches, to reduce the capacitance between the metal lines. A deposition process for a dielectric material between metal lines is tuned so that air gaps are formed within the dielectric material, in areas between metal lines. The dielectric material is also deposited between the upper portions of the metal lines, closing the air gaps from the top. The dielectric material is highly selective to a subsequent via etch, so that the dielectric material near the tops of the metal lines acts as an etch stop and prevents punch through into the air gaps.

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.