Patents by Inventor Akshith VASANTH

Akshith VASANTH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Applying chip select for memory device identification and power management control
    Patent number: 11335395
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale
  • APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MANAGEMENT CONTROL
    Publication number: 20210020224
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Application
    Filed: October 2, 2020
    Publication date: January 21, 2021
    Inventors: Christopher E. COX, Kuljit S. BAINS, Christopher P. MOZAK, James A. McCALL, Akshith VASANTH, Bill NALE
  • Applying chip select for memory device identification and power management control
    Patent number: 10839887
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale
  • APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MANAGEMENT CONTROL
    Publication number: 20190392886
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Application
    Filed: October 30, 2017
    Publication date: December 26, 2019
    Inventors: Christopher E. COX, Kuljit S. BAINS, Christopher P. MOZAK, James A. McCALL, Akshith VASANTH, Bill NALE