Patents by Inventor Al Davis

Al Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10799366
    Abstract: Intervertebral devices and systems, and methods of their use, are disclosed having configurations suitable for placement between two adjacent vertebrae, replacing the functionality of the disc therebetween. Intervertebral devices and systems contemplated herein are implantable devices intended for replacement of a vertebral disc, which may have deteriorated due to disease for example. The intervertebral devices and systems are configured to allow for ample placement of therapeutic agents therein, including bone growth enhancement material, which may lead to better fusion between adjacent vertebral bones. The intervertebral devices and systems are configured for use in minimally invasive procedures, if desired.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: October 13, 2020
    Assignee: Expanding Innovations, Inc.
    Inventors: John Davis, Al Mirel, Mark Dias
  • Patent number: 10691375
    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Paolo Faraboschi, Daniel Gmach, Yuan Chen, Al Davis, Adit Madan
  • Patent number: 10613949
    Abstract: In some examples, a node of a computing system may include a failure identification engine and a failure response engine. The failure identification engine may identify a failure condition for a system function of the node and the failure response engine may store a failure indication in a shared memory to trigger takeover of the system function by a different node of the computing system.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Charles Johnson, Harumi Kuno, Al Davis
  • Patent number: 10491545
    Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nicholas George McDonald, Gary Gostin, Darel N. Emmot, Gregg B. Lesartre, Al Davis, Derek Alan Sherlock
  • Publication number: 20180343210
    Abstract: Examples relate to virtual channel routing in networks considering VC actions to be performed by the packets while routed through the network. A packet is received at an input port of a network device of a network and an output port and a VC action is determined from a routing table associated to the input port based on a packet's destination network device. A VC mask is determined from a Virtual Channel Action Table (VCAT), associated to the routing table, based on a packet's ingress VC and the VC action. A particular VC among the set of VCs defined in the VC mask is selected and the packet is routed to the destination network device using the output port and the particular VC.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: Nicholas George McDonald, Gary Gostin, Darel N. Emmot, Gregg B. Lesartre, Al Davis, Derek Alan Sherlock
  • Publication number: 20180293144
    Abstract: In some examples, a node of a computing system may include a failure identification engine and a failure response engine. The failure identification engine may identify a failure condition for a system function of the node and the failure response engine may store a failure indication in a shared memory to trigger takeover of the system function by a different node of the computing system.
    Type: Application
    Filed: September 24, 2015
    Publication date: October 11, 2018
    Inventors: Charles Johnson, Harumi Kuno, Al Davis
  • Publication number: 20180004456
    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.
    Type: Application
    Filed: January 30, 2015
    Publication date: January 4, 2018
    Inventors: Vanish Talwar, Paolo Faraboschi, Daniel Gmach, Yuan Chen, Al Davis, Adit Madan
  • Patent number: 9847949
    Abstract: Examples disclosed herein relate to receiving, by a scheduler, a request for a window during which to send a data packet through a crossbar. Transmission of the data packet is dependent upon a pool of transmission credits. The scheduler determines whether the pool of transmission credits is sufficient for transmitting the data packet, and when it is determined that the pool of transmission credits is insufficient, the scheduler determines whether to block the request or to speculatively arbitrate the window based on a value of a speculative request counter.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nicholas George McDonald, Al Davis
  • Patent number: 8537677
    Abstract: Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: September 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jung Ho Ahn, Nathan Binkert, Al Davis, Moray McLaren, Robert Schreiber
  • Patent number: 8064739
    Abstract: Examples of a computer system packaged in a three-dimensional stack of dies are described. The package includes an electrical die and an optical die coupled to and stacked with the electrical die. The electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals. The electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports. Additionally, the packaging can be configured to provide structural support against insertion forces for external optical connections.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: November 22, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathan Binkert, Norm Jouppi, Al Davis, Raymond Beausoleil
  • Patent number: 7945128
    Abstract: Various embodiments of the present invention are directed to optical-based barrier methods and systems for synchronizing processing of two or more threads. In one method embodiment of a barrier method, each thread can be processed by a different processing element. The method comprises transmitting a lightwave along a waveguide that is optically coupled to each of the processing elements. Each processing element that processes a thread turns on diverter capable of diverting substantially all of the lightwave from the waveguide. Each processing element that completes processing of a thread turns off a corresponding diverter. A barrier is reached when all of the processing elements have turned off the corresponding diverters and discontinued diverting a portion of the lightwave from the waveguide.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: May 17, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathan Binkert, Al Davis, Robert Schraiber, Dana Vantrease
  • Publication number: 20110085561
    Abstract: Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 14, 2011
    Inventors: Jung Ho Ahn, Nathan Binkert, Al Davis, Moray McLaren, Robert Schreiber
  • Publication number: 20090103855
    Abstract: Examples of a computer system packaged in a three-dimensional stack of dies are described. The package includes an electrical die and an optical die coupled to and stacked with the electrical die. The electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals. The electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports. Additionally, the packaging can be configured to provide structural support against insertion forces for external optical connections.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 23, 2009
    Inventors: Nathan Binkert, Norm Jouppi, Al Davis, Raymond Beausoleil
  • Publication number: 20080285165
    Abstract: Various embodiments of a system and method for producing a thin film filter are disclosed.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Inventors: Kuohua (Angus) Wu, Al Davis, David L. Erickson