Patents by Inventor Ala Uddin

Ala Uddin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR DETERMINING PATIENT DISEASE LOAD
    Publication number: 20210319885
    Abstract: Systems and methods are provided for collecting, aggregating, and visualizing resource availability information including patient disease load for one or more medical facilities. In one example, a method includes determining, based on one or more test results of one or more tests for a disease included in a data stream from a medical facility and further based on an amount of time since the one or more tests were conducted, whether a patient suspected of having the disease is positive, negative, or under investigation for the disease; and updating one or more resource availability graphical user interfaces (GUIs) based on the determination.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 14, 2021
    Inventors: Andrew Day, Jeffrey Richardson Terry, Siyun Hur, Ala Uddin, Mark Grum, Younan Fakhouri, Gaurav Sahariya, Gabriella Devine, Sean Lister
  • Techniques for testing memory circuits
    Patent number: 7984344
    Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Chin Hai Ang, Tze Sin Tan, Ala-Uddin Ismail, Siew Ling Yeoh
  • Techniques for testing memory circuits
    Patent number: 7761754
    Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: July 20, 2010
    Assignee: Altera Corporation
    Inventors: Chin Hai Ang, Tze Sin Tan, Ala-Uddin Ismail, Siew Ling Yeoh