Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0·q?1 q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj-1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

Abstract: The method for elliptic curve scalar multiplication may provide several countermeasures to protect scalar multiplication of a private key k by a point P to produce the product kP from power analysis attacks. First, the private key, k, is partitioned into a plurality of key partitions, which are processed in a random order, the resulting points being accumulated to produce the scalar product kP. Second, in each partition, the encoding is randomly selected to occur in binary form or in Non-Adjacent Form (NAF), with the direction of bit inspection being randomly assigned between most-to-least and least-to-most. Third, in each partition, each zero in the key may randomly perform a dummy point addition operation in addition to the doubling operation. The method may be implemented in software, smart cards, circuits, processors, or application specific integrated circuits (ASICs) designed to carry out the method.

Abstract: The method for elliptic curve scalar multiplication may provide several countermeasures to protect scalar multiplication of a private key k by a point P to produce the product kP from power analysis attacks. First, the private key, k, is partitioned into a plurality of key partitions, which are processed in a random order, the resulting points being accumulated to produce the scalar product kP. Second, in each partition, the encoding is randomly selected to occur in binary form or in Non-Adjacent Form (NAF), with the direction of bit inspection being randomly assigned between most-to-least and least-to-most. Third, in each partition, each zero in the key may randomly perform a dummy point addition operation in addition to the doubling operation. The method may be implemented in software, smart cards, circuits, processors, or application specific integrated circuits (ASICs) designed to carry out the method.

Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0·q?1 q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj?1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

Abstract: The method for elliptic curve scalar multiplication may provide several countermeasures to protect scalar multiplication of a private key k by a point P to produce the product kP from power analysis attacks. First, the private key, k, is partitioned into a plurality of key partitions, which are processed in a random order, the resulting points being accumulated to produce the scalar product kP. Second, in each partition, the encoding is randomly selected to occur in binary form or in Non-Adjacent Form (NAF), with the direction of bit inspection being randomly assigned between most-to-least and least-to-most. Third, in each partition, each zero in the key may randomly perform a dummy point addition operation in addition to the doubling operation. The method may be implemented in software, smart cards, circuits, processors, or application specific integrated circuits (ASICs) designed to carry out the method.

Abstract: The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q?1q?2 . . . q?n), then the algorithm provides for computing S = AB D to yield a w-bit quotient Q and w-bit remainder R by: (1) determining the next quotient digit q?j using a quotient digit selection function; (2) generating the product q?jD; and (3) performing the triple addition of rRj?1, (?q?jD) and b - ( j - 1 ) ? ( A r ) where R0=b?1Ar?1. The recurrence relation may be implemented with carry-save adders for computation using bitwise logical operators (AND, OR, XOR).

Abstract: The method for high-speed modulo multiplication is a method for multiplying integers A and B modulus N that is optimized for high speed implementation in an electronic device, which may be implemented in software, but is preferably implemented in hardware. The multiplication is performed on devices requiring no more than k+2 bits, where k is the number of significant bits in A, B, and N. The method computes the running product biiAW, where AW is either A when the previous running product is negative, or W when the previous running product is positive, W being the N-conjugate of A formed by A?N. On each iteration, the magnitude of the running product is reduced by a scaling factor no greater than 2N according to the state of the two most significant bits of the running product when carry propagate adders are used.

Abstract: An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.