Patents by Inventor Alain Aurand

Alain Aurand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip-flop with a metal programmable initialization logic state
    Patent number: 10804885
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • FLIP-FLOP WITH A METAL PROGRAMMABLE INITIALIZATION LOGIC STATE
    Publication number: 20200112301
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Application
    Filed: October 16, 2019
    Publication date: April 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Sylvain ENGELS, Alain AURAND, Etienne MAURIN
  • Flip-flop with a metal programmable initialization logic state
    Patent number: 10505522
    Abstract: A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin