Patents by Inventor Alain Caron
Alain Caron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9408240Abstract: There is disclosed a system and method for choosing between different Communication Initiation Request (CIR) channels in a mobile communications system when there are multiple CIR channels amongst which to choose. Additionally, there is disclosed a system and method for exploiting a Transmission Control Protocol (TCP) connection usage pattern that is characterized by periods of inactivity.Type: GrantFiled: August 30, 2006Date of Patent: August 2, 2016Assignee: Synchronica plcInventors: Alain Caron, Sylvain Legault, Haraldur Thorkelsson, Felix-Etienne Trepanier, Teresa Hunkeler, Jean Regnier
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Patent number: 9088416Abstract: A computing system, method and product comprising a server, a mobile device comprising a client interconnected with the server via a data network, the client identified by a credential which is unavailable to the client and an intermediate node interconnected to the client and the server via the data network wherein the credential is available to the intermediate node. Upon reception of a service request from the client at a first server address the server redirects the client to transmit the service request to a second server address via the intermediate node together with a token, wherein the intermediate node appends a credential identifying the client to the redirected service request and the token and relays the redirected service request, the token and the credential to the second server address.Type: GrantFiled: November 24, 2006Date of Patent: July 21, 2015Assignee: Synchronica plcInventors: Nikolai Grigoriev, Haraldur Thorkelsson, Sylvain Legault, Alain Caron
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Patent number: 8812597Abstract: There is described an interconnect hub for routing an Instant Message (IM) or related communication between a sending IM device in a first IM community and a recipient IM device in one of a plurality of potential second IM communities. The interconnect hub comprises a router for determining the destination of IM communications and routing the IM communications to the intended recipient, a search function for finding the service provider providing IM services to the user identifier, and a cache comprising a plurality of records associating user identifiers with corresponding service providers (mobile or Internet). When the IM communication is received by the interconnect hub, the router examines the recipient user identifier, accesses the cache keying on the recipient user identifier, retrieves the service provider associated with the recipient user identifier, and forwards the IM communication to the associated service provider for delivery to the intended recipient.Type: GrantFiled: February 19, 2008Date of Patent: August 19, 2014Assignee: Synchronica plcInventors: Gwenael Le Bodic, Alain Caron, Jean Regnier, Manuel Laflamme
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Patent number: 8629562Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: GrantFiled: August 31, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Publication number: 20120326321Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: ApplicationFiled: August 31, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Patent number: 8288866Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: GrantFiled: January 25, 2011Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Publication number: 20110121456Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: ApplicationFiled: January 25, 2011Publication date: May 26, 2011Applicant: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Patent number: 7892885Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: GrantFiled: October 30, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Patent number: 7741153Abstract: Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro.Type: GrantFiled: October 30, 2007Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Publication number: 20090111215Abstract: Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Publication number: 20090108427Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Alain Caron, John Ulrich Knickerbocker
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Publication number: 20080307517Abstract: A computing system, method and product comprising a server, a mobile device comprising a client interconnected with the server via a data network, the client identified by a credential which is unavailable to the client and an intermediate node interconnected to the client and the server via the data network wherein the credential is available to the intermediate node. Upon reception of a service request from the client at a first server address the server redirects the client to transmit the service request to a second server address via the intermediate node together with a token, wherein the intermediate node appends a credential identifying the client to the redirected service request and the token and relays the redirected service request, the token and the credential to the second server address.Type: ApplicationFiled: November 24, 2006Publication date: December 11, 2008Inventors: Nikolai Grigoriev, Haraldur Thorkelsson, Sylvain Legault, Alain Caron
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Publication number: 20080263170Abstract: There is disclosed a system and method for choosing between different Communication Initiation Request (CIR) channels in a mobile communications system when there are multiple CIR channels amongst which to choose. Additionally, there is disclosed a system and method for exploiting a Transmission Control Protocol (TCP) connection usage pattern that is characterized by periods of inactivity.Type: ApplicationFiled: August 30, 2006Publication date: October 23, 2008Inventors: Alain Caron, Sylvain Legault, Haraldur Thorkelsson, Felix-Etienne Trepanier, Teresa Hunkeler, Jean Regnier
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Publication number: 20080201441Abstract: There is described an interconnect hub for routing an Instant Message (IM) or related communication between a sending IM device in a first IM community and a recipient IM device in one of a plurality of potential second IM communities. The interconnect hub comprises a router for determining the destination of IM communications and routing the IM communications to the intended recipient, a search function for finding the service provider providing IM services to the user identifier, and a cache comprising a plurality of records associating user identifiers with corresponding service providers (mobile or Internet). When the IM communication is received by the interconnect hub, the router examines the recipient user identifier, accesses the cache keying on the recipient user identifier, retrieves the service provider associated with the recipient user identifier, and forwards the IM communication to the associated service provider for delivery to the intended recipient.Type: ApplicationFiled: February 19, 2008Publication date: August 21, 2008Applicant: OZ Communications Inc.Inventors: Gwenael Le Bodic, Alain Caron, Jean Regnier, Manuel Laflamme
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Patent number: 7146596Abstract: An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.Type: GrantFiled: August 29, 2003Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Timothy W. Budell, Patrick H. Buffet, Alain Caron, James V. Crain, Jr., Douglas W. Kemerer, Donald S. Kent, Esmaeil Rahmati
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Patent number: 7017128Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.Type: GrantFiled: December 17, 2003Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
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Publication number: 20050050505Abstract: An integrated circuit chip (104) having a contact layer (136) that includes a plurality of Vdd, Vddx, ground and I/O contacts (116, 120, 124, 128) arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. An X-Y power grid (140) is located beneath the contact layer and includes metal layers (LM?) each having a plurality of wires (68) extending in one direction. The direction of the wires alternates from one metal layer to the next adjacent metal layer. A wiring layer (IM) is interposed between the contact layer and power grid layers to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires (144, 148, 152) located alternatingly with one another.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Bednar, Timothy Budell, Patrick Buffet, Alain Caron, James Crain, Douglas Kemerer, Donald Kent, Esmaeil Rahmati
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Publication number: 20040132229Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.Type: ApplicationFiled: December 17, 2003Publication date: July 8, 2004Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
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Patent number: 6703706Abstract: An electrical structure to optimize a signal wire structure. The electrical structure provides concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.Type: GrantFiled: January 8, 2002Date of Patent: March 9, 2004Assignee: International Business Machines CorporationInventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
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Publication number: 20030127728Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.Type: ApplicationFiled: January 8, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron