Abstract: An integrated circuit (IC) fabricated on a Silicon-On-Insulator (SOI) wafer, having a plurality of impedance elements cascoded in series, each impedance elements having a specified value. A subset of the impedance elements are arranged to bias a first tub at a specified very high voltage (VHV) multiplied by a first predetermined ratio. A further subset of the impedance elements are arranged to bias a second tub at VHV multiplied by a second predetermined ratio and each of the impedance elements are further arranged to bias a handle and a third surrounding tub at VHV multiplied by a third predetermined ratio. A method for designing an integrated circuit using fully dielectrically isolated processes which function reliably at higher operating voltages than that provided by the conventional processes.

Abstract: An integrated circuit (IC) fabricated on a Silicon-On-Insulator (SOI) wafer, having a plurality of impedance elements cascoded in series, each impedance elements having a specified value. A subset of the impedance elements are arranged to bias a first tub at a specified very high voltage (VHV) multiplied by a first predetermined ratio. A further subset of the impedance elements are arranged to bias a second tub at VHV multiplied by a second predetermined ratio and each of the impedance elements are further arranged to bias a handle and a third surrounding tub at VHV multiplied by a third predetermined ratio. A method for designing an integrated circuit using fully dielectrically isolated processes which function reliably at higher operating voltages than that provided by the conventional processes.

Abstract: A request that includes an indication of an execution context and data that represents executable code is obtained. An analysis of the data is initiated based on generating a first templatized representation of the executable code. A list of clearance indicators that indicate a blocking status associated with respective forms of templatized representations is accessed. A workflow policy is determined based on the accessing of the list of clearance indicators. The list of clearance indicators is updated, based on a result of the analysis of the data.

Abstract: A request that includes an indication of an execution context and data that represents executable code is obtained. An analysis of the data is initiated based on generating a first templatized representation of the executable code. A list of clearance indicators that indicate a blocking status associated with respective forms of templatized representations is accessed. A workflow policy is determined based on the accessing of the list of clearance indicators. The list of clearance indicators is updated, based on a result of the analysis of the data.

Abstract: A circuit arrangement and associated method for splitting current in a predetermined ratio between N sub-circuits, comprising means for splitting current at one end of a each sub-circuit and at least one device at the other end of each sub-circuit adapted to become forward biased and acts as a short to ground.

Abstract: A circuit arrangement and associated method for splitting current in a predetermined ratio between N sub-circuits, comprising means for splitting current at one end of a each sub-circuit and at least one device at the other end of each sub-circuit adapted to become forward biased and acts as a short to ground.

Abstract: A method of preparing semiconductor wafers with intrinsic gettering capability, comprises the steps of: carrying out a high temperature wet oxidation on a doped semiconductor wafer for between about 20 to 60 minutes to form an initial oxidation layer; heating said wafer at a moderate temperature in an inert atmosphere for about 1 to 4 hours to initiate formation of crystal nuclei; ramping up the temperature in said inert atmosphere to a temperature of at least about 850.degree. C. at a rate of about 1.degree.-10.degree. C./min.; and subsequently carrying out well diffusion on the wafer at a temperature of at least about 1000.degree. C.

Abstract: A semiconductor test chip for use in semiconductor fabrication fault analysis, comprises an n.times.m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row, the sources and drains of each row being independent, and within a column strips of conductive material of a second type form common gate electrodes such that each column of transistors can be turned on independently. An input circuit permits a predetermined bit pattern to be selectively applied to the inputs of the rows of transmission gate cells. A demultiplexer including output transmission gates is connected to respective outputs of the rows of the array for selectively addressing the output of each row of transmission gate cells.